Module d1_pac::ccu::dram_clk

DRAM Clock Register

Structs

• DRAM_CLK_SPEC
  DRAM Clock Register
• R
  Register dram_clk reader
• W
  Register dram_clk writer

Enums

• CLK_GATING_A
  Gating Clock
• CLK_SRC_SEL_A
  Clock Source Select
• DRAM_DIV2_A
  Factor N
• SDRCLK_UPD_A
  SDRCLK Configuration 0 Update

Type Aliases

• CLK_GATING_R
  Field clk_gating reader - Gating Clock
• CLK_GATING_W
  Field clk_gating writer - Gating Clock
• CLK_SRC_SEL_R
  Field clk_src_sel reader - Clock Source Select
• CLK_SRC_SEL_W
  Field clk_src_sel writer - Clock Source Select
• DRAM_DIV1_R
  Field dram_div1 reader - Factor M
• DRAM_DIV1_W
  Field dram_div1 writer - Factor M
• DRAM_DIV2_R
  Field dram_div2 reader - Factor N
• DRAM_DIV2_W
  Field dram_div2 writer - Factor N
• SDRCLK_UPD_R
  Field sdrclk_upd reader - SDRCLK Configuration 0 Update
• SDRCLK_UPD_W
  Field sdrclk_upd writer - SDRCLK Configuration 0 Update