Module d1_pac::ccu::pll_ddr_pat0_ctrl

PLL_DDR Pattern0 Control Register

Structs

• PLL_DDR_PAT0_CTRL_SPEC
  PLL_DDR Pattern0 Control Register
• R
  Register pll_ddr_pat0_ctrl reader
• W
  Register pll_ddr_pat0_ctrl writer

Enums

• FREQ_A
  Frequency
• SDM_CLK_SEL_A
  SDM Clock Select
• SPR_FREQ_MODE_A
  Spread Frequency Mode

Type Aliases

• FREQ_R
  Field freq reader - Frequency
• FREQ_W
  Field freq writer - Frequency
• SDM_CLK_SEL_R
  Field sdm_clk_sel reader - SDM Clock Select
• SDM_CLK_SEL_W
  Field sdm_clk_sel writer - SDM Clock Select
• SIG_DELT_PAT_EN_R
  Field sig_delt_pat_en reader - Sigma-Delta Pattern Enable
• SIG_DELT_PAT_EN_W
  Field sig_delt_pat_en writer - Sigma-Delta Pattern Enable
• SPR_FREQ_MODE_R
  Field spr_freq_mode reader - Spread Frequency Mode
• SPR_FREQ_MODE_W
  Field spr_freq_mode writer - Spread Frequency Mode
• WAVE_BOT_R
  Field wave_bot reader - Wave Bottom
• WAVE_BOT_W
  Field wave_bot writer - Wave Bottom
• WAVE_STEP_R
  Field wave_step reader - Wave Step
• WAVE_STEP_W
  Field wave_step writer - Wave Step