Module d1_pac::csic::csic_dma::csic_dma_pclk_stat

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CSIC DMA PCLK Statistic Register

Structs§

  • CSIC DMA PCLK Statistic Register
  • Register csic_dma_pclk_stat reader
  • Register csic_dma_pclk_stat writer

Type Aliases§

  • Field pclk_cnt_line_max reader - Indicates maximum pixel clock counter value for each line. Update at every vsync or framedone.
  • Field pclk_cnt_line_min reader - Indicates minimum pixel clock counter value for each line. Update at every vsync or framedone.