Module d1_pac::csic::csic_parser0::csic_prs_ncsic_rx_signal5_dly_adj

CSIC Parser NCSIC RX Signal5 Delay Adjust Register

Structs

• CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ_SPEC
  CSIC Parser NCSIC RX Signal5 Delay Adjust Register
• R
  Register csic_prs_ncsic_rx_signal5_dly_adj reader
• W
  Register csic_prs_ncsic_rx_signal5_dly_adj writer

Type Aliases

• D4_DLY_R
  Field d4_dly reader - D4_dly 32 Step for adjust, 1 step = 0.2 ns
• D4_DLY_W
  Field d4_dly writer - D4_dly 32 Step for adjust, 1 step = 0.2 ns
• D5_DLY_R
  Field d5_dly reader - D5_dly 32 Step for adjust, 1 step = 0.2 ns
• D5_DLY_W
  Field d5_dly writer - D5_dly 32 Step for adjust, 1 step = 0.2 ns
• D6_DLY_R
  Field d6_dly reader - D6_dly 32 Step for adjust, 1 step = 0.2 ns
• D6_DLY_W
  Field d6_dly writer - D6_dly 32 Step for adjust, 1 step = 0.2 ns
• D7_DLY_R
  Field d7_dly reader - D7_dly 32 Step for adjust, 1 step = 0.2 ns
• D7_DLY_W
  Field d7_dly writer - D7_dly 32 Step for adjust, 1 step = 0.2 ns