Module d1_pac::csic::csic_parser0::csic_prs_ncsic_rx_signal6_dly_adj

CSIC Parser NCSIC RX Signal6 Delay Adjust Register

Structs

• CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ_SPEC
  CSIC Parser NCSIC RX Signal6 Delay Adjust Register
• R
  Register csic_prs_ncsic_rx_signal6_dly_adj reader
• W
  Register csic_prs_ncsic_rx_signal6_dly_adj writer

Type Aliases

• D0_DLY_R
  Field d0_dly reader - D0_dly 32 Step for adjust, 1 step = 0.2 ns
• D0_DLY_W
  Field d0_dly writer - D0_dly 32 Step for adjust, 1 step = 0.2 ns
• D1_DLY_R
  Field d1_dly reader - D1_dly 32 Step for adjust, 1 step = 0.2 ns
• D1_DLY_W
  Field d1_dly writer - D1_dly 32 Step for adjust, 1 step = 0.2 ns
• D2_DLY_R
  Field d2_dly reader - D2_dly 32 Step for adjust, 1 step = 0.2 ns
• D2_DLY_W
  Field d2_dly writer - D2_dly 32 Step for adjust, 1 step = 0.2 ns
• D3_DLY_R
  Field d3_dly reader - D3_dly 32 Step for adjust, 1 step = 0.2 ns
• D3_DLY_W
  Field d3_dly writer - D3_dly 32 Step for adjust, 1 step = 0.2 ns