Module d1_pac::tpadc::tp_ctrl0

TP Control Register 0

Structs

• R
  Register tp_ctrl0 reader
• TP_CTRL0_SPEC
  TP Control Register 0
• W
  Register tp_ctrl0 writer

Enums

• ADC_CLK_DIVIDER_A
  ADC Clock Divider (CLK_IN)
• ADC_FIRST_DLY_MODE_A
  ADC First Convert Delay Mode Select
• FS_DIV_A
  ADC Sample Frequency Divider

Type Aliases

• ADC_CLK_DIVIDER_R
  Field adc_clk_divider reader - ADC Clock Divider (CLK_IN)
• ADC_CLK_DIVIDER_W
  Field adc_clk_divider writer - ADC Clock Divider (CLK_IN)
• ADC_FIRST_DLY_MODE_R
  Field adc_first_dly_mode reader - ADC First Convert Delay Mode Select
• ADC_FIRST_DLY_MODE_W
  Field adc_first_dly_mode writer - ADC First Convert Delay Mode Select
• ADC_FIRST_DLY_R
  Field adc_first_dly reader - ADC First Convert Delay Time (T_FCDT) Setting
• ADC_FIRST_DLY_W
  Field adc_first_dly writer - ADC First Convert Delay Time (T_FCDT) Setting
• FS_DIV_R
  Field fs_div reader - ADC Sample Frequency Divider
• FS_DIV_W
  Field fs_div writer - ADC Sample Frequency Divider
• TACQ_R
  Field tacq reader - Touch panel ADC acquire time
• TACQ_W
  Field tacq writer - Touch panel ADC acquire time