Struct d1_pac::audio_codec::adc::W

pub struct W(/* private fields */);

Register adc%s writer

Implementations

impl W

pub fn adc_iopmic(&mut self) -> ADC_IOPMIC_W<'_, 0>

Bits 0:1 - ADC OP MIC Bias Current Select

IOPADC is defined by ADC_REG<15:14> from 1 uA to 4 uA.

pub unsafe fn adc_iopsdm<const O: u8>(&mut self) -> ADC_IOPSDM_W<'_, O>

ADC OP SDM Bias Current Select [i]

IOPADC is defined by ADC_REG<15:14> from 1 uA to 4 uA.

pub fn adc_iopsdm2(&mut self) -> ADC_IOPSDM_W<'_, 4>

Bits 4:5 - ADC OP SDM Bias Current Select [i]

IOPADC is defined by ADC_REG<15:14> from 1 uA to 4 uA.

pub fn adc_iopsdm1(&mut self) -> ADC_IOPSDM_W<'_, 6>

Bits 6:7 - ADC OP SDM Bias Current Select [i]

IOPADC is defined by ADC_REG<15:14> from 1 uA to 4 uA.

pub fn adc_iopaaf(&mut self) -> ADC_IOPAAF_W<'_, 6>

Bits 6:7 - ADC OP AAF Bias Current Select

IOPADC is defined by ADC_REG<15:14> from 1 uA to 4 uA.

For example: ADC_REG<15:14> = 11, IOPADC = 4 uA

00: 1.50*4 uA = 6 uA

01: 1.75*4 uA = 7 uA

10: 2.00*4 uA = 8 uA

11: 2.25*4 uA = 9 uA

pub fn adc_pga_gain_ctrl(&mut self) -> ADC_PGA_GAIN_CTRL_W<'_, 8>

Bits 8:12 - ADC PGA gain settings:

0x0: 0 dB \t0x10: 21 dB

0x1: 6 dB \t0x11: 22 dB

0x2: 6 dB \t0x12: 23 dB

0x3: 6 dB \t0x13: 24 dB

0x4: 9 dB \t0x14: 25 dB

0x5: 10 dB\t0x15: 26 dB

0x6: 11 dB\t0x16: 27 dB

0x7: 12 dB\t0x17: 28 dB

0x8: 13 dB\t0x18: 29 dB

0x9: 14 dB\t0x19: 30 dB

0xA: 15 dB\t0x1A: 31 dB

0xB: 16 dB\t0x1B: 32 dB

0xC: 17 dB\t0x1C: 33 dB

0xD: 18 dB\t0x1D: 34 dB

0xE: 19 dB\t0x1E: 35 dB

0xF: 20 dB\t0x1F: 36 dB

pub fn iopadc(&mut self) -> IOPADC_W<'_, 14>

Bits 14:15 - ADC1-ADC3 Bias Current Select

pub fn adc_pga_in_vcm_ctrl(&mut self) -> ADC_PGA_IN_VCM_CTRL_W<'_, 16>

Bits 16:17 - ADC PGA Common-Mode Voltage Control

pub fn adc_pga_ctrl_rcm(&mut self) -> ADC_PGA_CTRL_RCM_W<'_, 18>

Bits 18:19 - ADC PGA Common Mode Input Impedance Control for MICIN

pub fn iopbuffer(&mut self) -> IOPBUFFER_W<'_, 20>

Bits 20:21 - PGA Vcm Buffer OP Bias Current Select

pub fn lineinlg(&mut self) -> LINEINLG_W<'_, 22>

Bit 22 - LINEINL Gain Control

pub fn lineinlen(&mut self) -> LINEINLEN_W<'_, 23>

Bit 23 - LINEINL Enable

pub fn dsm_dither_lvl(&mut self) -> DSM_DITHER_LVL_W<'_, 24>

Bits 24:25 - Dither Level Control (Dither level is positive ralated to the ctrl bits)

pub fn fminlg(&mut self) -> FMINLG_W<'_, 26>

Bit 26 - FMINL Gain Control

pub fn fminlen(&mut self) -> FMINLEN_W<'_, 27>

Bit 27 - FMINL Enable

pub fn mic_sin_en(&mut self) -> MIC_SIN_EN_W<'_, 28>

Bit 28 - MIC Single Input Enable

pub fn adc_d_itcher_c_ontrol(&mut self) -> ADC_D_ITCHER_C_ONTROL_W<'_, 29>

Bit 29 - Dither Control

pub fn mic_pga_en(&mut self) -> MIC_PGA_EN_W<'_, 30>

Bit 30 - MIC PGA Enable

pub fn adc_en(&mut self) -> ADC_EN_W<'_, 31>

Bit 31 - ADC Channel Enable

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<ADC_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<ADC_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<ADC_SPEC>> for W

fn from(writer: W<ADC_SPEC>) -> Self

Converts to this type from the input type.