Struct d1_pac::ccu::mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC

pub struct MBUS_MAT_CLK_GATING_SPEC;

MBUS Master Clock Gating Register

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see mbus_mat_clk_gating module

Trait Implementations

impl Readable for MBUS_MAT_CLK_GATING_SPEC

read() method returns mbus_mat_clk_gating::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for MBUS_MAT_CLK_GATING_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for MBUS_MAT_CLK_GATING_SPEC

reset() method sets mbus_mat_clk_gating to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <ccu::mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for MBUS_MAT_CLK_GATING_SPEC

write(|w| ..) method takes mbus_mat_clk_gating::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ccu::mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ccu::mbus_mat_clk_gating::MBUS_MAT_CLK_GATING_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1