Struct d1_pac::ccu::riscv_cfg_bgr::RISCV_CFG_BGR_SPEC

pub struct RISCV_CFG_BGR_SPEC;

RISC-V_CFG Bus Gating Reset Register

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see riscv_cfg_bgr module

Trait Implementations

impl Readable for RISCV_CFG_BGR_SPEC

read() method returns riscv_cfg_bgr::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for RISCV_CFG_BGR_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for RISCV_CFG_BGR_SPEC

reset() method sets riscv_cfg_bgr to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <ccu::riscv_cfg_bgr::RISCV_CFG_BGR_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for RISCV_CFG_BGR_SPEC

write(|w| ..) method takes riscv_cfg_bgr::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ccu::riscv_cfg_bgr::RISCV_CFG_BGR_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ccu::riscv_cfg_bgr::RISCV_CFG_BGR_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1