Struct d1_pac::ccu::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 119 fields
    pub pll_cpu_ctrl: PLL_CPU_CTRL,
    pub pll_ddr_ctrl: PLL_DDR_CTRL,
    pub pll_peri_ctrl: PLL_PERI_CTRL,
    pub pll_video0_ctrl: PLL_VIDEO0_CTRL,
    pub pll_video1_ctrl: PLL_VIDEO1_CTRL,
    pub pll_ve_ctrl: PLL_VE_CTRL,
    pub pll_audio0_ctrl: PLL_AUDIO0_CTRL,
    pub pll_audio1_ctrl: PLL_AUDIO1_CTRL,
    pub pll_ddr_pat0_ctrl: PLL_DDR_PAT0_CTRL,
    pub pll_ddr_pat1_ctrl: PLL_DDR_PAT1_CTRL,
    pub pll_peri_pat0_ctrl: PLL_PERI_PAT0_CTRL,
    pub pll_peri_pat1_ctrl: PLL_PERI_PAT1_CTRL,
    pub pll_video0_pat0_ctrl: PLL_VIDEO0_PAT0_CTRL,
    pub pll_video0_pat1_ctrl: PLL_VIDEO0_PAT1_CTRL,
    pub pll_video1_pat0_ctrl: PLL_VIDEO1_PAT0_CTRL,
    pub pll_video1_pat1_ctrl: PLL_VIDEO1_PAT1_CTRL,
    pub pll_ve_pat0_ctrl: PLL_VE_PAT0_CTRL,
    pub pll_ve_pat1_ctrl: PLL_VE_PAT1_CTRL,
    pub pll_audio0_pat0_ctrl: PLL_AUDIO0_PAT0_CTRL,
    pub pll_audio0_pat1_ctrl: PLL_AUDIO0_PAT1_CTRL,
    pub pll_audio1_pat0_ctrl: PLL_AUDIO1_PAT0_CTRL,
    pub pll_audio1_pat1_ctrl: PLL_AUDIO1_PAT1_CTRL,
    pub pll_cpu_bias: PLL_CPU_BIAS,
    pub pll_ddr_bias: PLL_DDR_BIAS,
    pub pll_peri_bias: PLL_PERI_BIAS,
    pub pll_video0_bias: PLL_VIDEO0_BIAS,
    pub pll_video1_bias: PLL_VIDEO1_BIAS,
    pub pll_ve_bias: PLL_VE_BIAS,
    pub pll_audio0_bias: PLL_AUDIO0_BIAS,
    pub pll_audio1_bias: PLL_AUDIO1_BIAS,
    pub pll_cpu_tun: PLL_CPU_TUN,
    pub cpu_axi_cfg: CPU_AXI_CFG,
    pub cpu_gating: CPU_GATING,
    pub psi_clk: PSI_CLK,
    pub apb_clk: [APB_CLK; 2],
    pub mbus_clk: MBUS_CLK,
    pub de_clk: DE_CLK,
    pub de_bgr: DE_BGR,
    pub di_clk: DI_CLK,
    pub di_bgr: DI_BGR,
    pub g2d_clk: G2D_CLK,
    pub g2d_bgr: G2D_BGR,
    pub ce_clk: CE_CLK,
    pub ce_bgr: CE_BGR,
    pub ve_clk: VE_CLK,
    pub ve_bgr: VE_BGR,
    pub dma_bgr: DMA_BGR,
    pub msgbox_bgr: MSGBOX_BGR,
    pub spinlock_bgr: SPINLOCK_BGR,
    pub hstimer_bgr: HSTIMER_BGR,
    pub avs_clk: AVS_CLK,
    pub dbgsys_bgr: DBGSYS_BGR,
    pub pwm_bgr: PWM_BGR,
    pub iommu_bgr: IOMMU_BGR,
    pub dram_clk: DRAM_CLK,
    pub mbus_mat_clk_gating: MBUS_MAT_CLK_GATING,
    pub dram_bgr: DRAM_BGR,
    pub smhc0_clk: SMHC0_CLK,
    pub smhc1_clk: SMHC1_CLK,
    pub smhc2_clk: SMHC2_CLK,
    pub smhc_bgr: SMHC_BGR,
    pub uart_bgr: UART_BGR,
    pub twi_bgr: TWI_BGR,
    pub spi0_clk: SPI0_CLK,
    pub spi1_clk: SPI1_CLK,
    pub spi_bgr: SPI_BGR,
    pub emac_25m_clk: EMAC_25M_CLK,
    pub emac_bgr: EMAC_BGR,
    pub irtx_clk: IRTX_CLK,
    pub irtx_bgr: IRTX_BGR,
    pub gpadc_bgr: GPADC_BGR,
    pub ths_bgr: THS_BGR,
    pub i2s_clk: [I2S_CLK; 3],
    pub i2s2_asrc_clk: I2S2_ASRC_CLK,
    pub i2s_bgr: I2S_BGR,
    pub owa_tx_clk: OWA_TX_CLK,
    pub owa_rx_clk: OWA_RX_CLK,
    pub owa_bgr: OWA_BGR,
    pub dmic_clk: DMIC_CLK,
    pub dmic_bgr: DMIC_BGR,
    pub audio_codec_dac_clk: AUDIO_CODEC_DAC_CLK,
    pub audio_codec_adc_clk: AUDIO_CODEC_ADC_CLK,
    pub audio_codec_bgr: AUDIO_CODEC_BGR,
    pub usb0_clk: USB0_CLK,
    pub usb1_clk: USB1_CLK,
    pub usb_bgr: USB_BGR,
    pub lradc_bgr: LRADC_BGR,
    pub dpss_top_bgr: DPSS_TOP_BGR,
    pub dsi_clk: DSI_CLK,
    pub dsi_bgr: DSI_BGR,
    pub tconlcd_clk: TCONLCD_CLK,
    pub tconlcd_bgr: TCONLCD_BGR,
    pub tcontv_clk: TCONTV_CLK,
    pub tcontv_bgr: TCONTV_BGR,
    pub lvds_bgr: LVDS_BGR,
    pub tve_clk: TVE_CLK,
    pub tve_bgr: TVE_BGR,
    pub tvd_clk: TVD_CLK,
    pub tvd_bgr: TVD_BGR,
    pub ledc_clk: LEDC_CLK,
    pub ledc_bgr: LEDC_BGR,
    pub csi_clk: CSI_CLK,
    pub csi_master_clk: CSI_MASTER_CLK,
    pub csi_bgr: CSI_BGR,
    pub tpadc_clk: TPADC_CLK,
    pub tpadc_bgr: TPADC_BGR,
    pub dsp_clk: DSP_CLK,
    pub dsp_bgr: DSP_BGR,
    pub riscv_clk: RISCV_CLK,
    pub riscv_gating: RISCV_GATING,
    pub riscv_cfg_bgr: RISCV_CFG_BGR,
    pub pll_lock_dbg_ctrl: PLL_LOCK_DBG_CTRL,
    pub fre_det_ctrl: FRE_DET_CTRL,
    pub fre_up_lim: FRE_UP_LIM,
    pub fre_down_lim: FRE_DOWN_LIM,
    pub ccu_fan_gate: CCU_FAN_GATE,
    pub clk27m_fan: CLK27M_FAN,
    pub pclk_fan: PCLK_FAN,
    pub ccu_fan: CCU_FAN,
    /* private fields */
}

Expand description

Register block

Fields§

§pll_cpu_ctrl: PLL_CPU_CTRL

0x00 - PLL_CPU Control Register

§pll_ddr_ctrl: PLL_DDR_CTRL

0x10 - PLL_DDR Control Register

§pll_peri_ctrl: PLL_PERI_CTRL

0x20 - PLL_PERI Control Register

§pll_video0_ctrl: PLL_VIDEO0_CTRL

0x40 - PLL_VIDEO0 Control Register

§pll_video1_ctrl: PLL_VIDEO1_CTRL

0x48 - PLL_VIDEO1 Control Register

§pll_ve_ctrl: PLL_VE_CTRL

0x58 - PLL_VE Control Register

§pll_audio0_ctrl: PLL_AUDIO0_CTRL

0x78 - PLL_AUDIO0 Control Register

§pll_audio1_ctrl: PLL_AUDIO1_CTRL

0x80 - PLL_AUDIO1 Control Register

§pll_ddr_pat0_ctrl: PLL_DDR_PAT0_CTRL

0x110 - PLL_DDR Pattern0 Control Register

§pll_ddr_pat1_ctrl: PLL_DDR_PAT1_CTRL

0x114 - PLL_DDR Pattern1 Control Register

§pll_peri_pat0_ctrl: PLL_PERI_PAT0_CTRL

0x120 - PLL_PERI Pattern0 Control Register

§pll_peri_pat1_ctrl: PLL_PERI_PAT1_CTRL

0x124 - PLL_PERI Pattern1 Control Register

§pll_video0_pat0_ctrl: PLL_VIDEO0_PAT0_CTRL

0x140 - PLL_VIDEO0 Pattern0 Control Register

§pll_video0_pat1_ctrl: PLL_VIDEO0_PAT1_CTRL

0x144 - PLL_VIDEO0 Pattern1 Control Register

§pll_video1_pat0_ctrl: PLL_VIDEO1_PAT0_CTRL

0x148 - PLL_VIDEO1 Pattern0 Control Register

§pll_video1_pat1_ctrl: PLL_VIDEO1_PAT1_CTRL

0x14c - PLL_VIDEO1 Pattern1 Control Register

§pll_ve_pat0_ctrl: PLL_VE_PAT0_CTRL

0x158 - PLL_VE Pattern0 Control Register

§pll_ve_pat1_ctrl: PLL_VE_PAT1_CTRL

0x15c - PLL_VE Pattern1 Control Register

§pll_audio0_pat0_ctrl: PLL_AUDIO0_PAT0_CTRL

0x178 - PLL_AUDIO0 Pattern0 Control Register

§pll_audio0_pat1_ctrl: PLL_AUDIO0_PAT1_CTRL

0x17c - PLL_AUDIO0 Pattern1 Control Register

§pll_audio1_pat0_ctrl: PLL_AUDIO1_PAT0_CTRL

0x180 - PLL_AUDIO1 Pattern0 Control Register

§pll_audio1_pat1_ctrl: PLL_AUDIO1_PAT1_CTRL

0x184 - PLL_AUDIO1 Pattern1 Control Register

§pll_cpu_bias: PLL_CPU_BIAS

0x300 - PLL_CPU Bias Register

§pll_ddr_bias: PLL_DDR_BIAS

0x310 - PLL_DDR Bias Register

§pll_peri_bias: PLL_PERI_BIAS

0x320 - PLL_PERI Bias Register

§pll_video0_bias: PLL_VIDEO0_BIAS

0x340 - PLL_VIDEO0 Bias Register

§pll_video1_bias: PLL_VIDEO1_BIAS

0x348 - PLL_VIDEO1 Bias Register

§pll_ve_bias: PLL_VE_BIAS

0x358 - PLL_VE Bias Register

§pll_audio0_bias: PLL_AUDIO0_BIAS

0x378 - PLL_AUDIO0 Bias Register

§pll_audio1_bias: PLL_AUDIO1_BIAS

0x380 - PLL_AUDIO1 Bias Register

§pll_cpu_tun: PLL_CPU_TUN

0x400 - PLL_CPU Tuning Register

§cpu_axi_cfg: CPU_AXI_CFG

0x500 - CPU_AXI Configuration Register

§cpu_gating: CPU_GATING

0x504 - CPU_GATING Configuration Register

§psi_clk: PSI_CLK

0x510 - PSI Clock Register

§apb_clk: [APB_CLK; 2]

0x520..0x528 - APB Clock Register

§mbus_clk: MBUS_CLK

0x540 - MBUS Clock Register

§de_clk: DE_CLK

0x600 - DE Clock Register

§de_bgr: DE_BGR

0x60c - DE Bus Gating Reset Register

§di_clk: DI_CLK

0x620 - DI Clock Register

§di_bgr: DI_BGR

0x62c - DI Bus Gating Reset Register

§g2d_clk: G2D_CLK

0x630 - G2D Clock Register

§g2d_bgr: G2D_BGR

0x63c - G2D Bus Gating Reset Register

§ce_clk: CE_CLK

0x680 - CE Clock Register

§ce_bgr: CE_BGR

0x68c - CE Bus Gating Reset Register

§ve_clk: VE_CLK

0x690 - VE Clock Register

§ve_bgr: VE_BGR

0x69c - VE Bus Gating Reset Register

§dma_bgr: DMA_BGR

0x70c - DMA Bus Gating Reset Register

§msgbox_bgr: MSGBOX_BGR

0x71c - MSGBOX Bus Gating Reset Register

§spinlock_bgr: SPINLOCK_BGR

0x72c - SPINLOCK Bus Gating Reset Register

§hstimer_bgr: HSTIMER_BGR

0x73c - HSTIMER Bus Gating Reset Register

§avs_clk: AVS_CLK

0x740 - AVS Clock Register

§dbgsys_bgr: DBGSYS_BGR

0x78c - DBGSYS Bus Gating Reset Register

§pwm_bgr: PWM_BGR

0x7ac - PWM Bus Gating Reset Register

§iommu_bgr: IOMMU_BGR

0x7bc - IOMMU Bus Gating Reset Register

§dram_clk: DRAM_CLK

0x800 - DRAM Clock Register

§mbus_mat_clk_gating: MBUS_MAT_CLK_GATING

0x804 - MBUS Master Clock Gating Register

§dram_bgr: DRAM_BGR

0x80c - DRAM Bus Gating Reset Register

§smhc0_clk: SMHC0_CLK

0x830 - SMHC0 Clock Register

§smhc1_clk: SMHC1_CLK

0x834 - SMHC1 Clock Register

§smhc2_clk: SMHC2_CLK

0x838 - SMHC2 Clock Register

§smhc_bgr: SMHC_BGR

0x84c - SMHC Bus Gating Reset Register

§uart_bgr: UART_BGR

0x90c - UART Bus Gating Reset Register

§twi_bgr: TWI_BGR

0x91c - TWI Bus Gating Reset Register

§spi0_clk: SPI0_CLK

0x940 - SPI0 Clock Register

§spi1_clk: SPI1_CLK

0x944 - SPI1 Clock Register

§spi_bgr: SPI_BGR

0x96c - SPI Bus Gating Reset Register

§emac_25m_clk: EMAC_25M_CLK

0x970 - EMAC_25M Clock Register

§emac_bgr: EMAC_BGR

0x97c - EMAC Bus Gating Reset Register

§irtx_clk: IRTX_CLK

0x9c0 - IRTX Clock Register

§irtx_bgr: IRTX_BGR

0x9cc - IRTX Bus Gating Reset Register

§gpadc_bgr: GPADC_BGR

0x9ec - GPADC Bus Gating Reset Register

§ths_bgr: THS_BGR

0x9fc - THS Bus Gating Reset Register

§i2s_clk: [I2S_CLK; 3]

0xa10..0xa1c - I2S Clock Register

§i2s2_asrc_clk: I2S2_ASRC_CLK

0xa1c - I2S2_ASRC Clock Register

§i2s_bgr: I2S_BGR

0xa20 - I2S Bus Gating Reset Register

§owa_tx_clk: OWA_TX_CLK

0xa24 - OWA_TX Clock Register

§owa_rx_clk: OWA_RX_CLK

0xa28 - OWA_RX Clock Register

§owa_bgr: OWA_BGR

0xa2c - OWA Bus Gating Reset Register

§dmic_clk: DMIC_CLK

0xa40 - DMIC Clock Register

§dmic_bgr: DMIC_BGR

0xa4c - DMIC Bus Gating Reset Register

§audio_codec_dac_clk: AUDIO_CODEC_DAC_CLK

0xa50 - AUDIO_CODEC_DAC Clock Register

§audio_codec_adc_clk: AUDIO_CODEC_ADC_CLK

0xa54 - AUDIO_CODEC_ADC Clock Register

§audio_codec_bgr: AUDIO_CODEC_BGR

0xa5c - AUDIO_CODEC Bus Gating Reset Register

§usb0_clk: USB0_CLK

0xa70 - USB0 Clock Register

§usb1_clk: USB1_CLK

0xa74 - USB1 Clock Register

§usb_bgr: USB_BGR

0xa8c - USB Bus Gating Reset Register

§lradc_bgr: LRADC_BGR

0xa9c - LRADC Bus Gating Reset Register

§dpss_top_bgr: DPSS_TOP_BGR

0xabc - DPSS_TOP Bus Gating Reset Register

§dsi_clk: DSI_CLK

0xb24 - DSI Clock Register

§dsi_bgr: DSI_BGR

0xb4c - DSI Bus Gating Reset Register

§tconlcd_clk: TCONLCD_CLK

0xb60 - TCONLCD Clock Register

§tconlcd_bgr: TCONLCD_BGR

0xb7c - TCONLCD Bus Gating Reset Register

§tcontv_clk: TCONTV_CLK

0xb80 - TCONTV Clock Register

§tcontv_bgr: TCONTV_BGR

0xb9c - TCONTV Bus Gating Reset Register

§lvds_bgr: LVDS_BGR

0xbac - LVDS Bus Gating Reset Register

§tve_clk: TVE_CLK

0xbb0 - TVE Clock Register

§tve_bgr: TVE_BGR

0xbbc - TVE Bus Gating Reset Register

§tvd_clk: TVD_CLK

0xbc0 - TVD Clock Register

§tvd_bgr: TVD_BGR

0xbdc - TVD Bus Gating Reset Register

§ledc_clk: LEDC_CLK

0xbf0 - LEDC Clock Register

§ledc_bgr: LEDC_BGR

0xbfc - LEDC Bus Gating Reset Register

§csi_clk: CSI_CLK

0xc04 - CSI Clock Register

§csi_master_clk: CSI_MASTER_CLK

0xc08 - CSI Master Clock Register

§csi_bgr: CSI_BGR

0xc1c - CSI Bus Gating Reset Register

§tpadc_clk: TPADC_CLK

0xc50 - TPADC Clock Register

§tpadc_bgr: TPADC_BGR

0xc5c - TPADC Bus Gating Reset Register

§dsp_clk: DSP_CLK

0xc70 - DSP Clock Register

§dsp_bgr: DSP_BGR

0xc7c - DSP Bus Gating Reset Register

§riscv_clk: RISCV_CLK

0xd00 - RISC-V Clock Register

§riscv_gating: RISCV_GATING

0xd04 - RISC-V GATING Configuration Register

§riscv_cfg_bgr: RISCV_CFG_BGR

0xd0c - RISC-V_CFG Bus Gating Reset Register

§pll_lock_dbg_ctrl: PLL_LOCK_DBG_CTRL

0xf04 - PLL Lock Debug Control Register

§fre_det_ctrl: FRE_DET_CTRL

0xf08 - Frequency Detect Control Register

§fre_up_lim: FRE_UP_LIM

0xf0c - Frequency Up Limit Register

§fre_down_lim: FRE_DOWN_LIM

0xf10 - Frequency Down Limit Register

§ccu_fan_gate: CCU_FAN_GATE

0xf30 - CCU FANOUT CLOCK GATE Register

§clk27m_fan: CLK27M_FAN

0xf34 - CLK27M FANOUT Register

§pclk_fan: PCLK_FAN

0xf38 - PCLK FANOUT Register

§ccu_fan: CCU_FAN

0xf3c - CCU FANOUT Register

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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Struct d1_pac::ccu::RegisterBlock

Fields§

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for T
where U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for T
where U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct d1_pac::ccu::RegisterBlockCopy item path

Fields§

Auto Trait Implementations§

impl !Freeze for RegisterBlock

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct d1_pac::ccu::RegisterBlock

impl<T> Any for T
where T: 'static + ?Sized,

impl<T> Borrow<T> for T
where T: ?Sized,

impl<T> BorrowMut<T> for T
where T: ?Sized,

impl<T, U> Into<U> for T
where U: From<T>,

impl<T, U> TryFrom<U> for T
where U: Into<T>,

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,