Struct d1_pac::cir_tx::cir_txint::R

pub struct R(/* private fields */);

Register cir_txint reader

Implementations

impl R

pub fn tpei_tui_en(&self) -> TPEI_TUI_EN_R

Bit 0 - Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse

pub fn tai_en(&self) -> TAI_EN_R

Bit 1 - TX FIFO Available Interrupt Enable

pub fn drq_en(&self) -> DRQ_EN_R

Bit 2 - TX FIFO DMA Enable

When it is set to ‘1’, the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails.

Methods from Deref<Target = R<CIR_TXINT_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CIR_TXINT_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CIR_TXINT_SPEC>> for R

fn from(reader: R<CIR_TXINT_SPEC>) -> Self

Converts to this type from the input type.