Struct d1_pac::cir_tx::cir_txint::W

pub struct W(/* private fields */);

Register cir_txint writer

Implementations

impl W

pub fn tpei_tui_en(&mut self) -> TPEI_TUI_EN_W<'_, 0>

Bit 0 - Transmit Packet End Interrupt Enable for Cyclical Pulse / Transmitter FIFO Underrun Interrupt Enable for Non-cyclical Pulse

pub fn tai_en(&mut self) -> TAI_EN_W<'_, 1>

Bit 1 - TX FIFO Available Interrupt Enable

pub fn drq_en(&mut self) -> DRQ_EN_W<'_, 2>

Bit 2 - TX FIFO DMA Enable

When it is set to ‘1’, the TX FIFO DRQ is asserted if the number of the transmitting data in the FIFO is less than the RAL. The DRQ is de-asserted when the condition fails.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CIR_TXINT_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CIR_TXINT_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CIR_TXINT_SPEC>> for W

fn from(writer: W<CIR_TXINT_SPEC>) -> Self

Converts to this type from the input type.