Module d1_pac::csic::csic_dma::csic_dma_frm_cnt
source · Expand description
CSIC DMA Frame Counter Register
Structs§
- CSIC DMA Frame Counter Register
- Register
csic_dma_frm_cntreader - Register
csic_dma_frm_cntwriter
Type Aliases§
- Field
frm_cnt_clrreader - When the bit set to 1, Frame cnt is cleared to 0. - Field
frm_cnt_clrwriter - When the bit set to 1, Frame cnt is cleared to 0. - Field
frm_cntreader - Counter value of frame. When frame done comes, the internal counter value add 1, and when the reg full, it is cleared to 0 . When parser sent a sync signal, it is cleared to 0. - Field
pclk_dma_clr_distancereader - Frame cnt clear cycle - Field
pclk_dma_clr_distancewriter - Frame cnt clear cycle