Struct d1_pac::csic::csic_dma::csic_dma_int_en::R

pub struct R(/* private fields */);

Register csic_dma_int_en reader

Implementations

impl R

pub fn cd_int_en(&self) -> CD_INT_EN_R

Bit 0 - Capture done

Indicates the CSI has completed capturing the image data. For still capture, the bit is set when one frame data has been written to buffer. For video capture, the bit is set when the last frame has been written to buffer after video capture has been disabled. For CCIR656 interface, if the output format is frame planar YCbCr 420 mode, the frame end means the field2 end, the other frame end means field end.

pub fn fd_int_en(&self) -> FD_INT_EN_R

Bit 1 - Frame done

Indicates the CSI has finished capturing an image frame. Applies to video capture mode. The bit is set after each completed frame capturing data is written to buffer as long as video capture remains enabled.

pub fn fifo0_of_int_en(&self) -> FIFO0_OF_INT_EN_R

Bit 2 - FIFO 0 overflow

The bit is set when the FIFO 0 became overflow.

pub fn fifo1_of_int_en(&self) -> FIFO1_OF_INT_EN_R

Bit 3 - FIFO 1 overflow

The bit is set when the FIFO 1 became overflow.

pub fn fifo2_of_int_en(&self) -> FIFO2_OF_INT_EN_R

Bit 4 - FIFO 2 overflow

The bit is set when the FIFO 2 became overflow.

pub fn lc_int_en(&self) -> LC_INT_EN_R

Bit 5 - Line counter flag The bit is set when the specific line has been written to dram every frame. The line number is set in the line counter register.

pub fn hb_of_int_en(&self) -> HB_OF_INT_EN_R

Bit 6 - Hblank FIFO overflow The bit is set when 3 FIFOs still overflow after the hblank.

pub fn vs_int_en(&self) -> VS_INT_EN_R

Bit 7 - vsync flag

The bit is set when vsync come. And at this time load the buffer address for the coming frame. So after this irq come, changing the buffer address could only effect next frame

pub fn clr_frame_cnt_int_en(&self) -> CLR_FRAME_CNT_INT_EN_R

Bit 11 - Set a INT when clear Frame cnt.

pub fn video_input_to_int_en(&self) -> VIDEO_INPUT_TO_INT_EN_R

Bit 12 - Set an INT when no video input exceeds the setting threshold time

pub fn buf_addr_fifo_int_en(&self) -> BUF_ADDR_FIFO_INT_EN_R

Bit 13 - Set an INT when content in BUF Address FIFO less than CSIC_DMA_BUFA_FIFO_THRESHOLD, only use in BUF Address FIFO MODE.

pub fn stored_frm_cnt_int_en(&self) -> STORED_FRM_CNT_INT_EN_R

Bit 14 - Set an INT when the value of CSIC_DMA_STORED_FRM_CNT reaches CSIC_DMA_STORED_FRM_THRESHOLD, only use in BUF Address FIFO MODE.

pub fn frm_lost_int_en(&self) -> FRM_LOST_INT_EN_R

Bit 15 - Set an INT when frame starts with empty Buffer Address FIFO, only use in BUF Address FIFO MODE.

Methods from Deref<Target = R<CSIC_DMA_INT_EN_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CSIC_DMA_INT_EN_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CSIC_DMA_INT_EN_SPEC>> for R

fn from(reader: R<CSIC_DMA_INT_EN_SPEC>) -> Self

Converts to this type from the input type.