Struct d1_pac::csic::csic_dma::CSIC_DMA

source · 
#[repr(C)]
pub struct CSIC_DMA {
Show 30 fields
    pub csic_dma_en: CSIC_DMA_EN,
    pub csic_dma_cfg: CSIC_DMA_CFG,
    pub csic_dma_hsize: CSIC_DMA_HSIZE,
    pub csic_dma_vsize: CSIC_DMA_VSIZE,
    pub csic_dma_f0_bufa: CSIC_DMA_F0_BUFA,
    pub csic_dma_f0_bufa_result: CSIC_DMA_F0_BUFA_RESULT,
    pub csic_dma_f1_bufa: CSIC_DMA_F1_BUFA,
    pub csic_dma_f1_bufa_result: CSIC_DMA_F1_BUFA_RESULT,
    pub csic_dma_f2_bufa: CSIC_DMA_F2_BUFA,
    pub csic_dma_f2_bufa_result: CSIC_DMA_F2_BUFA_RESULT,
    pub csic_dma_buf_len: CSIC_DMA_BUF_LEN,
    pub csic_dma_flip_size: CSIC_DMA_FLIP_SIZE,
    pub csic_dma_vi_to_th0: CSIC_DMA_VI_TO_TH0,
    pub csic_dma_vi_to_th1: CSIC_DMA_VI_TO_TH1,
    pub csic_dma_vi_to_cnt_val: CSIC_DMA_VI_TO_CNT_VAL,
    pub csic_dma_cap_sta: CSIC_DMA_CAP_STA,
    pub csic_dma_int_en: CSIC_DMA_INT_EN,
    pub csic_dma_int_sta: CSIC_DMA_INT_STA,
    pub csic_dma_line_cnt: CSIC_DMA_LINE_CNT,
    pub csic_dma_frm_cnt: CSIC_DMA_FRM_CNT,
    pub csic_dma_frm_clk_cnt: CSIC_DMA_FRM_CLK_CNT,
    pub csic_dma_acc_itnl_clk_cnt: CSIC_DMA_ACC_ITNL_CLK_CNT,
    pub csic_dma_fifo_stat: CSIC_DMA_FIFO_STAT,
    pub csic_dma_fifo_thrs: CSIC_DMA_FIFO_THRS,
    pub csic_dma_pclk_stat: CSIC_DMA_PCLK_STAT,
    pub csic_dma_buf_addr_fifo_entry: [CSIC_DMA_BUF_ADDR_FIFO_ENTRY; 3],
    pub csic_dma_buf_th: CSIC_DMA_BUF_TH,
    pub csic_dma_buf_addr_fifo_con: CSIC_DMA_BUF_ADDR_FIFO_CON,
    pub csic_dma_stored_frm_cnt: CSIC_DMA_STORED_FRM_CNT,
    pub csic_feature: CSIC_FEATURE,
    /* private fields */

}
Expand description

Register block

Fields§

§csic_dma_en: CSIC_DMA_EN

0x00 - CSIC DMA Enable Register

§csic_dma_cfg: CSIC_DMA_CFG

0x04 - CSIC DMA Configuration Register

§csic_dma_hsize: CSIC_DMA_HSIZE

0x10 - CSIC DMA Horizontal Size Register

§csic_dma_vsize: CSIC_DMA_VSIZE

0x14 - CSIC DMA Vertical Size Register

§csic_dma_f0_bufa: CSIC_DMA_F0_BUFA

0x20 - CSIC DMA FIFO 0 Output Buffer-A Address Register

§csic_dma_f0_bufa_result: CSIC_DMA_F0_BUFA_RESULT

0x24 - CSIC DMA FIFO 0 Output Buffer-A Address Result Register

§csic_dma_f1_bufa: CSIC_DMA_F1_BUFA

0x28 - CSIC DMA FIFO 1 Output Buffer-A Address Register

§csic_dma_f1_bufa_result: CSIC_DMA_F1_BUFA_RESULT

0x2c - CSIC DMA FIFO 1 Output Buffer-A Address Result Register

§csic_dma_f2_bufa: CSIC_DMA_F2_BUFA

0x30 - CSIC DMA FIFO 2 Output Buffer-A Address Register

§csic_dma_f2_bufa_result: CSIC_DMA_F2_BUFA_RESULT

0x34 - CSIC DMA FIFO 2 Output Buffer-A Address Result Register

§csic_dma_buf_len: CSIC_DMA_BUF_LEN

0x38 - CSIC DMA Buffer Length Register

§csic_dma_flip_size: CSIC_DMA_FLIP_SIZE

0x3c - CSIC DMA Flip Size Register

§csic_dma_vi_to_th0: CSIC_DMA_VI_TO_TH0

0x40 - CSIC DMA Video Input Timeout Threshold0 Register

§csic_dma_vi_to_th1: CSIC_DMA_VI_TO_TH1

0x44 - CSIC DMA Video Input Timeout Threshold1 Register

§csic_dma_vi_to_cnt_val: CSIC_DMA_VI_TO_CNT_VAL

0x48 - CSIC DMA Video Input Timeout Counter Value Register

§csic_dma_cap_sta: CSIC_DMA_CAP_STA

0x4c - CSIC DMA Capture Status Register

§csic_dma_int_en: CSIC_DMA_INT_EN

0x50 - CSIC DMA Interrupt Enable Register

§csic_dma_int_sta: CSIC_DMA_INT_STA

0x54 - CSIC DMA Interrupt Status Register

§csic_dma_line_cnt: CSIC_DMA_LINE_CNT

0x58 - CSIC DMA LINE Counter Register

§csic_dma_frm_cnt: CSIC_DMA_FRM_CNT

0x5c - CSIC DMA Frame Counter Register

§csic_dma_frm_clk_cnt: CSIC_DMA_FRM_CLK_CNT

0x60 - CSIC DMA Frame Clock Counter Register

§csic_dma_acc_itnl_clk_cnt: CSIC_DMA_ACC_ITNL_CLK_CNT

0x64 - CSIC DMA Accumulated And Internal Clock Counter Register

§csic_dma_fifo_stat: CSIC_DMA_FIFO_STAT

0x68 - CSIC DMA FIFO Statistic Register

§csic_dma_fifo_thrs: CSIC_DMA_FIFO_THRS

0x6c - CSIC DMA FIFO Threshold Register

§csic_dma_pclk_stat: CSIC_DMA_PCLK_STAT

0x70 - CSIC DMA PCLK Statistic Register

§csic_dma_buf_addr_fifo_entry: [CSIC_DMA_BUF_ADDR_FIFO_ENTRY; 3]

0x80..0x8c - CSIC DMA BUF Address FIFO[i] Entry Register

§csic_dma_buf_th: CSIC_DMA_BUF_TH

0x8c - CSIC DMA BUF Threshold Register

§csic_dma_buf_addr_fifo_con: CSIC_DMA_BUF_ADDR_FIFO_CON

0x90 - CSIC DMA BUF Address FIFO Content Register

§csic_dma_stored_frm_cnt: CSIC_DMA_STORED_FRM_CNT

0x94 - CSIC DMA Stored Frame Counter Register

§csic_feature: CSIC_FEATURE

0x1f4 - CSIC DMA Feature List Register

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