Module d1_pac::csic::csic_parser0::csic_prs_ncsic_rx_signal0_dly_adj

CSIC Parser NCSIC RX Signal0 Delay Adjust Register

Structs

• CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ_SPEC
  CSIC Parser NCSIC RX Signal0 Delay Adjust Register
• R
  Register csic_prs_ncsic_rx_signal0_dly_adj reader
• W
  Register csic_prs_ncsic_rx_signal0_dly_adj writer

Type Aliases

• FILED_DLY_R
  Field filed_dly reader - Filed_dly 32 Step for adjust, 1 step = 0.2 ns
• FILED_DLY_W
  Field filed_dly writer - Filed_dly 32 Step for adjust, 1 step = 0.2 ns
• HSYNC_DLY_R
  Field hsync_dly reader - Hsync_dly 32 Step for adjust, 1 step = 0.2 ns
• HSYNC_DLY_W
  Field hsync_dly writer - Hsync_dly 32 Step for adjust, 1 step = 0.2 ns
• PCLK_DLY_R
  Field pclk_dly reader - Pclk_dly 32 Step for adjust, 1 step = 0.2 ns
• PCLK_DLY_W
  Field pclk_dly writer - Pclk_dly 32 Step for adjust, 1 step = 0.2 ns
• VSYNC_DLY_R
  Field vsync_dly reader - Vsync_dly 32 Step for adjust, 1 step = 0.2 ns
• VSYNC_DLY_W
  Field vsync_dly writer - Vsync_dly 32 Step for adjust, 1 step = 0.2 ns