Struct d1_pac::csic::csic_parser0::prs_ncsic_if_cfg::R

pub struct R(/* private fields */);

Register prs_ncsic_if_cfg reader

Implementations

impl R

pub fn csi_if(&self) -> CSI_IF_R

Bits 0:4

pub fn input_seq(&self) -> INPUT_SEQ_R

Bits 6:7 - Input data sequence, only valid for YUV422 and YUV420 input format

pub fn if_data_width(&self) -> IF_DATA_WIDTH_R

Bits 8:10

pub fn seq_8plus2(&self) -> SEQ_8PLUS2_R

Bits 11:12 - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual CSI data bus according to these sequences

pub fn ddr_sample_mode_en(&self) -> DDR_SAMPLE_MODE_EN_R

Bit 13

pub fn field_dt_mode(&self) -> FIELD_DT_MODE_R

Bits 14:15 - only valid when CSI_IF is YUB and source type is interlaced

pub fn clk_pol(&self) -> CLK_POL_R

Bit 16 - Data clock type

pub fn href_pol(&self) -> HREF_POL_R

Bit 17 - Href polarity

This register is not applied to CCIR656 interface

pub fn vref_pol(&self) -> VREF_POL_R

Bit 18 - Vref polarity

This register is not applied to CCIR656 interface

pub fn field(&self) -> FIELD_R

Bit 19 - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)

pub fn source_type(&self) -> SOURCE_TYPE_R

Bits 20:23 - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3

pub fn field_dt_pclk_shift(&self) -> FIELD_DT_PCLK_SHIFT_R

Bits 24:27 - Only for vsync detected field mode, the odd field permitted pclk

shift = 4 * FIELD_DT_PCLK_SHIFT

pub fn yuv420_line_order(&self) -> YUV420_LINE_ORDER_R

Bit 31

Methods from Deref<Target = R<PRS_NCSIC_IF_CFG_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<PRS_NCSIC_IF_CFG_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<PRS_NCSIC_IF_CFG_SPEC>> for R

fn from(reader: R<PRS_NCSIC_IF_CFG_SPEC>) -> Self

Converts to this type from the input type.