Struct d1_pac::csic::csic_parser0::prs_ncsic_if_cfg::W
source · pub struct W(/* private fields */);
Expand description
Register prs_ncsic_if_cfg
writer
Implementations§
source§impl W
impl W
sourcepub fn input_seq(&mut self) -> INPUT_SEQ_W<'_, 6>
pub fn input_seq(&mut self) -> INPUT_SEQ_W<'_, 6>
Bits 6:7 - Input data sequence, only valid for YUV422 and YUV420 input format
sourcepub fn if_data_width(&mut self) -> IF_DATA_WIDTH_W<'_, 8>
pub fn if_data_width(&mut self) -> IF_DATA_WIDTH_W<'_, 8>
Bits 8:10
sourcepub fn seq_8plus2(&mut self) -> SEQ_8PLUS2_W<'_, 11>
pub fn seq_8plus2(&mut self) -> SEQ_8PLUS2_W<'_, 11>
Bits 11:12 - When select IF_DATA_WIDTH to be 8+2bit, odd/even pixel byte at CSI-D[11:4] will be rearranged to D[11:2]+2’b0 at the actual CSI data bus according to these sequences
sourcepub fn ddr_sample_mode_en(&mut self) -> DDR_SAMPLE_MODE_EN_W<'_, 13>
pub fn ddr_sample_mode_en(&mut self) -> DDR_SAMPLE_MODE_EN_W<'_, 13>
Bit 13
sourcepub fn field_dt_mode(&mut self) -> FIELD_DT_MODE_W<'_, 14>
pub fn field_dt_mode(&mut self) -> FIELD_DT_MODE_W<'_, 14>
Bits 14:15 - only valid when CSI_IF is YUB and source type is interlaced
sourcepub fn href_pol(&mut self) -> HREF_POL_W<'_, 17>
pub fn href_pol(&mut self) -> HREF_POL_W<'_, 17>
Bit 17 - Href polarity
This register is not applied to CCIR656 interface
sourcepub fn vref_pol(&mut self) -> VREF_POL_W<'_, 18>
pub fn vref_pol(&mut self) -> VREF_POL_W<'_, 18>
Bit 18 - Vref polarity
This register is not applied to CCIR656 interface
sourcepub fn field(&mut self) -> FIELD_W<'_, 19>
pub fn field(&mut self) -> FIELD_W<'_, 19>
Bit 19 - Field polarity (For YUV HV timing) / Field sequence (For BT656 timing)
sourcepub fn source_type(&mut self) -> SOURCE_TYPE_W<'_, 20>
pub fn source_type(&mut self) -> SOURCE_TYPE_W<'_, 20>
Bits 20:23 - Bit 20-23 corresponding to the SRC_TYPEs for channel 0-3
sourcepub fn field_dt_pclk_shift(&mut self) -> FIELD_DT_PCLK_SHIFT_W<'_, 24>
pub fn field_dt_pclk_shift(&mut self) -> FIELD_DT_PCLK_SHIFT_W<'_, 24>
Bits 24:27 - Only for vsync detected field mode, the odd field permitted pclk
shift = 4 * FIELD_DT_PCLK_SHIFT
sourcepub fn yuv420_line_order(&mut self) -> YUV420_LINE_ORDER_W<'_, 31>
pub fn yuv420_line_order(&mut self) -> YUV420_LINE_ORDER_W<'_, 31>
Bit 31