Struct d1_pac::csic::csic_parser0::CSIC_PARSER0

source · 
#[repr(C)]
pub struct CSIC_PARSER0 {
Show 48 fields
    pub prs_en: PRS_EN,
    pub prs_ncsic_if_cfg: PRS_NCSIC_IF_CFG,
    pub prs_cap: PRS_CAP,
    pub csic_prs_signal_sta: CSIC_PRS_SIGNAL_STA,
    pub csic_prs_ncsic_bt656_head_cfg: CSIC_PRS_NCSIC_BT656_HEAD_CFG,
    pub prs_ch0_infmt: PRS_CH_INFMT,
    pub prs_ch0_output_hsize: PRS_CH_OUTPUT_HSIZE,
    pub prs_ch0_output_vsize: PRS_CH_OUTPUT_VSIZE,
    pub prs_ch0_input_para0: PRS_CH_INPUT_PARA0,
    pub prs_ch0_input_para1: PRS_CH_INPUT_PARA1,
    pub prs_ch0_input_para2: PRS_CH_INPUT_PARA2,
    pub prs_ch0_input_para3: PRS_CH_INPUT_PARA3,
    pub prs_ch0_int_en: PRS_CH_INT_EN,
    pub prs_ch0_int_sta: PRS_CH_INT_STA,
    pub prs_ch00_line_time: PRS_CH0_LINE_TIME,
    pub prs_ch1_infmt: PRS_CH_INFMT,
    pub prs_ch1_output_hsize: PRS_CH_OUTPUT_HSIZE,
    pub prs_ch1_output_vsize: PRS_CH_OUTPUT_VSIZE,
    pub prs_ch1_input_para0: PRS_CH_INPUT_PARA0,
    pub prs_ch1_input_para1: PRS_CH_INPUT_PARA1,
    pub prs_ch1_input_para2: PRS_CH_INPUT_PARA2,
    pub prs_ch1_input_para3: PRS_CH_INPUT_PARA3,
    pub prs_ch1_int_en: PRS_CH_INT_EN,
    pub prs_ch1_int_sta: PRS_CH_INT_STA,
    pub prs_ch10_line_time: PRS_CH0_LINE_TIME,
    pub prs_ch2_infmt: PRS_CH_INFMT,
    pub prs_ch2_output_hsize: PRS_CH_OUTPUT_HSIZE,
    pub prs_ch2_output_vsize: PRS_CH_OUTPUT_VSIZE,
    pub prs_ch2_input_para0: PRS_CH_INPUT_PARA0,
    pub prs_ch2_input_para1: PRS_CH_INPUT_PARA1,
    pub prs_ch2_input_para2: PRS_CH_INPUT_PARA2,
    pub prs_ch2_input_para3: PRS_CH_INPUT_PARA3,
    pub prs_ch2_int_en: PRS_CH_INT_EN,
    pub prs_ch2_int_sta: PRS_CH_INT_STA,
    pub prs_ch20_line_time: PRS_CH0_LINE_TIME,
    pub prs_ch3_infmt: PRS_CH_INFMT,
    pub prs_ch3_output_hsize: PRS_CH_OUTPUT_HSIZE,
    pub prs_ch3_output_vsize: PRS_CH_OUTPUT_VSIZE,
    pub prs_ch3_input_para0: PRS_CH_INPUT_PARA0,
    pub prs_ch3_input_para1: PRS_CH_INPUT_PARA1,
    pub prs_ch3_input_para2: PRS_CH_INPUT_PARA2,
    pub prs_ch3_input_para3: PRS_CH_INPUT_PARA3,
    pub prs_ch3_int_en: PRS_CH_INT_EN,
    pub prs_ch3_int_sta: PRS_CH_INT_STA,
    pub prs_ch30_line_time: PRS_CH0_LINE_TIME,
    pub csic_prs_ncsic_rx_signal0_dly_adj: CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ,
    pub csic_prs_ncsic_rx_signal5_dly_adj: CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ,
    pub csic_prs_ncsic_rx_signal6_dly_adj: CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ,
    /* private fields */

}
Expand description

Register block

Fields§

§prs_en: PRS_EN

0x00 - Parser Enable Register

§prs_ncsic_if_cfg: PRS_NCSIC_IF_CFG

0x04 - Parser NCSIC Interface Configuration Register

§prs_cap: PRS_CAP

0x0c - Parser Capture Register

§csic_prs_signal_sta: CSIC_PRS_SIGNAL_STA

0x10 - CSIC Parser Signal Status Register

§csic_prs_ncsic_bt656_head_cfg: CSIC_PRS_NCSIC_BT656_HEAD_CFG

0x14 - CSIC Parser NCSIC BT656 Header Configuration Register

§prs_ch0_infmt: PRS_CH_INFMT

0x24 - Parser Channel[i] Input Format Register

§prs_ch0_output_hsize: PRS_CH_OUTPUT_HSIZE

0x28 - Parser Channel[i] Output Horizontal Size Register

§prs_ch0_output_vsize: PRS_CH_OUTPUT_VSIZE

0x2c - Parser Channel[i] Output Vertical Size Register

§prs_ch0_input_para0: PRS_CH_INPUT_PARA0

0x30 - Parser Channel[i] Input Parameter0 Register

§prs_ch0_input_para1: PRS_CH_INPUT_PARA1

0x34 - Parser Channel[i] Input Parameter1 Register

§prs_ch0_input_para2: PRS_CH_INPUT_PARA2

0x38 - Parser Channel[i] Input Parameter2 Register

§prs_ch0_input_para3: PRS_CH_INPUT_PARA3

0x3c - Parser Channel[i] Input Parameter3 Register

§prs_ch0_int_en: PRS_CH_INT_EN

0x40 - Parser Channel[i] Interrupt Enable Register

§prs_ch0_int_sta: PRS_CH_INT_STA

0x44 - Parser Channel[i] Interrupt Status Register

§prs_ch00_line_time: PRS_CH0_LINE_TIME

0x48 - Parser Channel[i] Line Time Register

§prs_ch1_infmt: PRS_CH_INFMT

0x124 - Parser Channel[i] Input Format Register

§prs_ch1_output_hsize: PRS_CH_OUTPUT_HSIZE

0x128 - Parser Channel[i] Output Horizontal Size Register

§prs_ch1_output_vsize: PRS_CH_OUTPUT_VSIZE

0x12c - Parser Channel[i] Output Vertical Size Register

§prs_ch1_input_para0: PRS_CH_INPUT_PARA0

0x130 - Parser Channel[i] Input Parameter0 Register

§prs_ch1_input_para1: PRS_CH_INPUT_PARA1

0x134 - Parser Channel[i] Input Parameter1 Register

§prs_ch1_input_para2: PRS_CH_INPUT_PARA2

0x138 - Parser Channel[i] Input Parameter2 Register

§prs_ch1_input_para3: PRS_CH_INPUT_PARA3

0x13c - Parser Channel[i] Input Parameter3 Register

§prs_ch1_int_en: PRS_CH_INT_EN

0x140 - Parser Channel[i] Interrupt Enable Register

§prs_ch1_int_sta: PRS_CH_INT_STA

0x144 - Parser Channel[i] Interrupt Status Register

§prs_ch10_line_time: PRS_CH0_LINE_TIME

0x148 - Parser Channel[i] Line Time Register

§prs_ch2_infmt: PRS_CH_INFMT

0x224 - Parser Channel[i] Input Format Register

§prs_ch2_output_hsize: PRS_CH_OUTPUT_HSIZE

0x228 - Parser Channel[i] Output Horizontal Size Register

§prs_ch2_output_vsize: PRS_CH_OUTPUT_VSIZE

0x22c - Parser Channel[i] Output Vertical Size Register

§prs_ch2_input_para0: PRS_CH_INPUT_PARA0

0x230 - Parser Channel[i] Input Parameter0 Register

§prs_ch2_input_para1: PRS_CH_INPUT_PARA1

0x234 - Parser Channel[i] Input Parameter1 Register

§prs_ch2_input_para2: PRS_CH_INPUT_PARA2

0x238 - Parser Channel[i] Input Parameter2 Register

§prs_ch2_input_para3: PRS_CH_INPUT_PARA3

0x23c - Parser Channel[i] Input Parameter3 Register

§prs_ch2_int_en: PRS_CH_INT_EN

0x240 - Parser Channel[i] Interrupt Enable Register

§prs_ch2_int_sta: PRS_CH_INT_STA

0x244 - Parser Channel[i] Interrupt Status Register

§prs_ch20_line_time: PRS_CH0_LINE_TIME

0x248 - Parser Channel[i] Line Time Register

§prs_ch3_infmt: PRS_CH_INFMT

0x324 - Parser Channel[i] Input Format Register

§prs_ch3_output_hsize: PRS_CH_OUTPUT_HSIZE

0x328 - Parser Channel[i] Output Horizontal Size Register

§prs_ch3_output_vsize: PRS_CH_OUTPUT_VSIZE

0x32c - Parser Channel[i] Output Vertical Size Register

§prs_ch3_input_para0: PRS_CH_INPUT_PARA0

0x330 - Parser Channel[i] Input Parameter0 Register

§prs_ch3_input_para1: PRS_CH_INPUT_PARA1

0x334 - Parser Channel[i] Input Parameter1 Register

§prs_ch3_input_para2: PRS_CH_INPUT_PARA2

0x338 - Parser Channel[i] Input Parameter2 Register

§prs_ch3_input_para3: PRS_CH_INPUT_PARA3

0x33c - Parser Channel[i] Input Parameter3 Register

§prs_ch3_int_en: PRS_CH_INT_EN

0x340 - Parser Channel[i] Interrupt Enable Register

§prs_ch3_int_sta: PRS_CH_INT_STA

0x344 - Parser Channel[i] Interrupt Status Register

§prs_ch30_line_time: PRS_CH0_LINE_TIME

0x348 - Parser Channel[i] Line Time Register

§csic_prs_ncsic_rx_signal0_dly_adj: CSIC_PRS_NCSIC_RX_SIGNAL0_DLY_ADJ

0x500 - CSIC Parser NCSIC RX Signal0 Delay Adjust Register

§csic_prs_ncsic_rx_signal5_dly_adj: CSIC_PRS_NCSIC_RX_SIGNAL5_DLY_ADJ

0x514 - CSIC Parser NCSIC RX Signal5 Delay Adjust Register

§csic_prs_ncsic_rx_signal6_dly_adj: CSIC_PRS_NCSIC_RX_SIGNAL6_DLY_ADJ

0x518 - CSIC Parser NCSIC RX Signal6 Delay Adjust Register

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