Struct d1_pac::dmac::RegisterBlock

source ·
#[repr(C)]
pub struct RegisterBlock {
Show 182 fields pub dmac_irq_en0: DMAC_IRQ_EN0, pub dmac_irq_en1: DMAC_IRQ_EN1, pub dmac_irq_pend0: DMAC_IRQ_PEND0, pub dmac_irq_pend1: DMAC_IRQ_PEND1, pub dmac_auto_gate: DMAC_AUTO_GATE, pub dmac_sta: DMAC_STA, pub dmac_en0: DMAC_EN, pub dmac_pau0: DMAC_PAU, pub dmac_desc_addr0: DMAC_DESC_ADDR, pub dmac_cfg0: DMAC_CFG, pub dmac_cur_src0: DMAC_CUR_SRC, pub dmac_cur_dest0: DMAC_CUR_DEST, pub dmac_bcnt_left0: DMAC_BCNT_LEFT, pub dmac_para0: DMAC_PARA, pub dmac_mode0: DMAC_MODE, pub dmac_fdesc_addr0: DMAC_FDESC_ADDR, pub dmac_pkg_num0: DMAC_PKG_NUM, pub dmac_en1: DMAC_EN, pub dmac_pau1: DMAC_PAU, pub dmac_desc_addr1: DMAC_DESC_ADDR, pub dmac_cfg1: DMAC_CFG, pub dmac_cur_src1: DMAC_CUR_SRC, pub dmac_cur_dest1: DMAC_CUR_DEST, pub dmac_bcnt_left1: DMAC_BCNT_LEFT, pub dmac_para1: DMAC_PARA, pub dmac_mode1: DMAC_MODE, pub dmac_fdesc_addr1: DMAC_FDESC_ADDR, pub dmac_pkg_num1: DMAC_PKG_NUM, pub dmac_en2: DMAC_EN, pub dmac_pau2: DMAC_PAU, pub dmac_desc_addr2: DMAC_DESC_ADDR, pub dmac_cfg2: DMAC_CFG, pub dmac_cur_src2: DMAC_CUR_SRC, pub dmac_cur_dest2: DMAC_CUR_DEST, pub dmac_bcnt_left2: DMAC_BCNT_LEFT, pub dmac_para2: DMAC_PARA, pub dmac_mode2: DMAC_MODE, pub dmac_fdesc_addr2: DMAC_FDESC_ADDR, pub dmac_pkg_num2: DMAC_PKG_NUM, pub dmac_en3: DMAC_EN, pub dmac_pau3: DMAC_PAU, pub dmac_desc_addr3: DMAC_DESC_ADDR, pub dmac_cfg3: DMAC_CFG, pub dmac_cur_src3: DMAC_CUR_SRC, pub dmac_cur_dest3: DMAC_CUR_DEST, pub dmac_bcnt_left3: DMAC_BCNT_LEFT, pub dmac_para3: DMAC_PARA, pub dmac_mode3: DMAC_MODE, pub dmac_fdesc_addr3: DMAC_FDESC_ADDR, pub dmac_pkg_num3: DMAC_PKG_NUM, pub dmac_en4: DMAC_EN, pub dmac_pau4: DMAC_PAU, pub dmac_desc_addr4: DMAC_DESC_ADDR, pub dmac_cfg4: DMAC_CFG, pub dmac_cur_src4: DMAC_CUR_SRC, pub dmac_cur_dest4: DMAC_CUR_DEST, pub dmac_bcnt_left4: DMAC_BCNT_LEFT, pub dmac_para4: DMAC_PARA, pub dmac_mode4: DMAC_MODE, pub dmac_fdesc_addr4: DMAC_FDESC_ADDR, pub dmac_pkg_num4: DMAC_PKG_NUM, pub dmac_en5: DMAC_EN, pub dmac_pau5: DMAC_PAU, pub dmac_desc_addr5: DMAC_DESC_ADDR, pub dmac_cfg5: DMAC_CFG, pub dmac_cur_src5: DMAC_CUR_SRC, pub dmac_cur_dest5: DMAC_CUR_DEST, pub dmac_bcnt_left5: DMAC_BCNT_LEFT, pub dmac_para5: DMAC_PARA, pub dmac_mode5: DMAC_MODE, pub dmac_fdesc_addr5: DMAC_FDESC_ADDR, pub dmac_pkg_num5: DMAC_PKG_NUM, pub dmac_en6: DMAC_EN, pub dmac_pau6: DMAC_PAU, pub dmac_desc_addr6: DMAC_DESC_ADDR, pub dmac_cfg6: DMAC_CFG, pub dmac_cur_src6: DMAC_CUR_SRC, pub dmac_cur_dest6: DMAC_CUR_DEST, pub dmac_bcnt_left6: DMAC_BCNT_LEFT, pub dmac_para6: DMAC_PARA, pub dmac_mode6: DMAC_MODE, pub dmac_fdesc_addr6: DMAC_FDESC_ADDR, pub dmac_pkg_num6: DMAC_PKG_NUM, pub dmac_en7: DMAC_EN, pub dmac_pau7: DMAC_PAU, pub dmac_desc_addr7: DMAC_DESC_ADDR, pub dmac_cfg7: DMAC_CFG, pub dmac_cur_src7: DMAC_CUR_SRC, pub dmac_cur_dest7: DMAC_CUR_DEST, pub dmac_bcnt_left7: DMAC_BCNT_LEFT, pub dmac_para7: DMAC_PARA, pub dmac_mode7: DMAC_MODE, pub dmac_fdesc_addr7: DMAC_FDESC_ADDR, pub dmac_pkg_num7: DMAC_PKG_NUM, pub dmac_en8: DMAC_EN, pub dmac_pau8: DMAC_PAU, pub dmac_desc_addr8: DMAC_DESC_ADDR, pub dmac_cfg8: DMAC_CFG, pub dmac_cur_src8: DMAC_CUR_SRC, pub dmac_cur_dest8: DMAC_CUR_DEST, pub dmac_bcnt_left8: DMAC_BCNT_LEFT, pub dmac_para8: DMAC_PARA, pub dmac_mode8: DMAC_MODE, pub dmac_fdesc_addr8: DMAC_FDESC_ADDR, pub dmac_pkg_num8: DMAC_PKG_NUM, pub dmac_en9: DMAC_EN, pub dmac_pau9: DMAC_PAU, pub dmac_desc_addr9: DMAC_DESC_ADDR, pub dmac_cfg9: DMAC_CFG, pub dmac_cur_src9: DMAC_CUR_SRC, pub dmac_cur_dest9: DMAC_CUR_DEST, pub dmac_bcnt_left9: DMAC_BCNT_LEFT, pub dmac_para9: DMAC_PARA, pub dmac_mode9: DMAC_MODE, pub dmac_fdesc_addr9: DMAC_FDESC_ADDR, pub dmac_pkg_num9: DMAC_PKG_NUM, pub dmac_en10: DMAC_EN, pub dmac_pau10: DMAC_PAU, pub dmac_desc_addr10: DMAC_DESC_ADDR, pub dmac_cfg10: DMAC_CFG, pub dmac_cur_src10: DMAC_CUR_SRC, pub dmac_cur_dest10: DMAC_CUR_DEST, pub dmac_bcnt_left10: DMAC_BCNT_LEFT, pub dmac_para10: DMAC_PARA, pub dmac_mode10: DMAC_MODE, pub dmac_fdesc_addr10: DMAC_FDESC_ADDR, pub dmac_pkg_num10: DMAC_PKG_NUM, pub dmac_en11: DMAC_EN, pub dmac_pau11: DMAC_PAU, pub dmac_desc_addr11: DMAC_DESC_ADDR, pub dmac_cfg11: DMAC_CFG, pub dmac_cur_src11: DMAC_CUR_SRC, pub dmac_cur_dest11: DMAC_CUR_DEST, pub dmac_bcnt_left11: DMAC_BCNT_LEFT, pub dmac_para11: DMAC_PARA, pub dmac_mode11: DMAC_MODE, pub dmac_fdesc_addr11: DMAC_FDESC_ADDR, pub dmac_pkg_num11: DMAC_PKG_NUM, pub dmac_en12: DMAC_EN, pub dmac_pau12: DMAC_PAU, pub dmac_desc_addr12: DMAC_DESC_ADDR, pub dmac_cfg12: DMAC_CFG, pub dmac_cur_src12: DMAC_CUR_SRC, pub dmac_cur_dest12: DMAC_CUR_DEST, pub dmac_bcnt_left12: DMAC_BCNT_LEFT, pub dmac_para12: DMAC_PARA, pub dmac_mode12: DMAC_MODE, pub dmac_fdesc_addr12: DMAC_FDESC_ADDR, pub dmac_pkg_num12: DMAC_PKG_NUM, pub dmac_en13: DMAC_EN, pub dmac_pau13: DMAC_PAU, pub dmac_desc_addr13: DMAC_DESC_ADDR, pub dmac_cfg13: DMAC_CFG, pub dmac_cur_src13: DMAC_CUR_SRC, pub dmac_cur_dest13: DMAC_CUR_DEST, pub dmac_bcnt_left13: DMAC_BCNT_LEFT, pub dmac_para13: DMAC_PARA, pub dmac_mode13: DMAC_MODE, pub dmac_fdesc_addr13: DMAC_FDESC_ADDR, pub dmac_pkg_num13: DMAC_PKG_NUM, pub dmac_en14: DMAC_EN, pub dmac_pau14: DMAC_PAU, pub dmac_desc_addr14: DMAC_DESC_ADDR, pub dmac_cfg14: DMAC_CFG, pub dmac_cur_src14: DMAC_CUR_SRC, pub dmac_cur_dest14: DMAC_CUR_DEST, pub dmac_bcnt_left14: DMAC_BCNT_LEFT, pub dmac_para14: DMAC_PARA, pub dmac_mode14: DMAC_MODE, pub dmac_fdesc_addr14: DMAC_FDESC_ADDR, pub dmac_pkg_num14: DMAC_PKG_NUM, pub dmac_en15: DMAC_EN, pub dmac_pau15: DMAC_PAU, pub dmac_desc_addr15: DMAC_DESC_ADDR, pub dmac_cfg15: DMAC_CFG, pub dmac_cur_src15: DMAC_CUR_SRC, pub dmac_cur_dest15: DMAC_CUR_DEST, pub dmac_bcnt_left15: DMAC_BCNT_LEFT, pub dmac_para15: DMAC_PARA, pub dmac_mode15: DMAC_MODE, pub dmac_fdesc_addr15: DMAC_FDESC_ADDR, pub dmac_pkg_num15: DMAC_PKG_NUM, /* private fields */
}
Expand description

Register block

Fields§

§dmac_irq_en0: DMAC_IRQ_EN0

0x00 - DMAC IRQ Enable Register 0

§dmac_irq_en1: DMAC_IRQ_EN1

0x04 - DMAC IRQ Enable Register 1

§dmac_irq_pend0: DMAC_IRQ_PEND0

0x10 - DMAC IRQ Pending Register 0

§dmac_irq_pend1: DMAC_IRQ_PEND1

0x14 - DMAC IRQ Pending Register 1

§dmac_auto_gate: DMAC_AUTO_GATE

0x28 - DMAC Auto Gating Register

§dmac_sta: DMAC_STA

0x30 - DMAC Status Register

§dmac_en0: DMAC_EN

0x100 - DMAC Channel Enable Register

§dmac_pau0: DMAC_PAU

0x104 - DMAC Channel Pause Register

§dmac_desc_addr0: DMAC_DESC_ADDR

0x108 - DMAC Channel Start Address Register

§dmac_cfg0: DMAC_CFG

0x10c - DMAC Channel Configuration Register

§dmac_cur_src0: DMAC_CUR_SRC

0x110 - DMAC Channel Current Source Register

§dmac_cur_dest0: DMAC_CUR_DEST

0x114 - DMAC Channel Current Destination Register

§dmac_bcnt_left0: DMAC_BCNT_LEFT

0x118 - DMAC Channel Byte Counter Left Register

§dmac_para0: DMAC_PARA

0x11c - DMAC Channel Parameter Register

§dmac_mode0: DMAC_MODE

0x128 - DMAC Mode Register

§dmac_fdesc_addr0: DMAC_FDESC_ADDR

0x12c - DMAC Former Descriptor Address Register

§dmac_pkg_num0: DMAC_PKG_NUM

0x130 - DMAC Package Number Register

§dmac_en1: DMAC_EN

0x140 - DMAC Channel Enable Register

§dmac_pau1: DMAC_PAU

0x144 - DMAC Channel Pause Register

§dmac_desc_addr1: DMAC_DESC_ADDR

0x148 - DMAC Channel Start Address Register

§dmac_cfg1: DMAC_CFG

0x14c - DMAC Channel Configuration Register

§dmac_cur_src1: DMAC_CUR_SRC

0x150 - DMAC Channel Current Source Register

§dmac_cur_dest1: DMAC_CUR_DEST

0x154 - DMAC Channel Current Destination Register

§dmac_bcnt_left1: DMAC_BCNT_LEFT

0x158 - DMAC Channel Byte Counter Left Register

§dmac_para1: DMAC_PARA

0x15c - DMAC Channel Parameter Register

§dmac_mode1: DMAC_MODE

0x168 - DMAC Mode Register

§dmac_fdesc_addr1: DMAC_FDESC_ADDR

0x16c - DMAC Former Descriptor Address Register

§dmac_pkg_num1: DMAC_PKG_NUM

0x170 - DMAC Package Number Register

§dmac_en2: DMAC_EN

0x180 - DMAC Channel Enable Register

§dmac_pau2: DMAC_PAU

0x184 - DMAC Channel Pause Register

§dmac_desc_addr2: DMAC_DESC_ADDR

0x188 - DMAC Channel Start Address Register

§dmac_cfg2: DMAC_CFG

0x18c - DMAC Channel Configuration Register

§dmac_cur_src2: DMAC_CUR_SRC

0x190 - DMAC Channel Current Source Register

§dmac_cur_dest2: DMAC_CUR_DEST

0x194 - DMAC Channel Current Destination Register

§dmac_bcnt_left2: DMAC_BCNT_LEFT

0x198 - DMAC Channel Byte Counter Left Register

§dmac_para2: DMAC_PARA

0x19c - DMAC Channel Parameter Register

§dmac_mode2: DMAC_MODE

0x1a8 - DMAC Mode Register

§dmac_fdesc_addr2: DMAC_FDESC_ADDR

0x1ac - DMAC Former Descriptor Address Register

§dmac_pkg_num2: DMAC_PKG_NUM

0x1b0 - DMAC Package Number Register

§dmac_en3: DMAC_EN

0x1c0 - DMAC Channel Enable Register

§dmac_pau3: DMAC_PAU

0x1c4 - DMAC Channel Pause Register

§dmac_desc_addr3: DMAC_DESC_ADDR

0x1c8 - DMAC Channel Start Address Register

§dmac_cfg3: DMAC_CFG

0x1cc - DMAC Channel Configuration Register

§dmac_cur_src3: DMAC_CUR_SRC

0x1d0 - DMAC Channel Current Source Register

§dmac_cur_dest3: DMAC_CUR_DEST

0x1d4 - DMAC Channel Current Destination Register

§dmac_bcnt_left3: DMAC_BCNT_LEFT

0x1d8 - DMAC Channel Byte Counter Left Register

§dmac_para3: DMAC_PARA

0x1dc - DMAC Channel Parameter Register

§dmac_mode3: DMAC_MODE

0x1e8 - DMAC Mode Register

§dmac_fdesc_addr3: DMAC_FDESC_ADDR

0x1ec - DMAC Former Descriptor Address Register

§dmac_pkg_num3: DMAC_PKG_NUM

0x1f0 - DMAC Package Number Register

§dmac_en4: DMAC_EN

0x200 - DMAC Channel Enable Register

§dmac_pau4: DMAC_PAU

0x204 - DMAC Channel Pause Register

§dmac_desc_addr4: DMAC_DESC_ADDR

0x208 - DMAC Channel Start Address Register

§dmac_cfg4: DMAC_CFG

0x20c - DMAC Channel Configuration Register

§dmac_cur_src4: DMAC_CUR_SRC

0x210 - DMAC Channel Current Source Register

§dmac_cur_dest4: DMAC_CUR_DEST

0x214 - DMAC Channel Current Destination Register

§dmac_bcnt_left4: DMAC_BCNT_LEFT

0x218 - DMAC Channel Byte Counter Left Register

§dmac_para4: DMAC_PARA

0x21c - DMAC Channel Parameter Register

§dmac_mode4: DMAC_MODE

0x228 - DMAC Mode Register

§dmac_fdesc_addr4: DMAC_FDESC_ADDR

0x22c - DMAC Former Descriptor Address Register

§dmac_pkg_num4: DMAC_PKG_NUM

0x230 - DMAC Package Number Register

§dmac_en5: DMAC_EN

0x240 - DMAC Channel Enable Register

§dmac_pau5: DMAC_PAU

0x244 - DMAC Channel Pause Register

§dmac_desc_addr5: DMAC_DESC_ADDR

0x248 - DMAC Channel Start Address Register

§dmac_cfg5: DMAC_CFG

0x24c - DMAC Channel Configuration Register

§dmac_cur_src5: DMAC_CUR_SRC

0x250 - DMAC Channel Current Source Register

§dmac_cur_dest5: DMAC_CUR_DEST

0x254 - DMAC Channel Current Destination Register

§dmac_bcnt_left5: DMAC_BCNT_LEFT

0x258 - DMAC Channel Byte Counter Left Register

§dmac_para5: DMAC_PARA

0x25c - DMAC Channel Parameter Register

§dmac_mode5: DMAC_MODE

0x268 - DMAC Mode Register

§dmac_fdesc_addr5: DMAC_FDESC_ADDR

0x26c - DMAC Former Descriptor Address Register

§dmac_pkg_num5: DMAC_PKG_NUM

0x270 - DMAC Package Number Register

§dmac_en6: DMAC_EN

0x280 - DMAC Channel Enable Register

§dmac_pau6: DMAC_PAU

0x284 - DMAC Channel Pause Register

§dmac_desc_addr6: DMAC_DESC_ADDR

0x288 - DMAC Channel Start Address Register

§dmac_cfg6: DMAC_CFG

0x28c - DMAC Channel Configuration Register

§dmac_cur_src6: DMAC_CUR_SRC

0x290 - DMAC Channel Current Source Register

§dmac_cur_dest6: DMAC_CUR_DEST

0x294 - DMAC Channel Current Destination Register

§dmac_bcnt_left6: DMAC_BCNT_LEFT

0x298 - DMAC Channel Byte Counter Left Register

§dmac_para6: DMAC_PARA

0x29c - DMAC Channel Parameter Register

§dmac_mode6: DMAC_MODE

0x2a8 - DMAC Mode Register

§dmac_fdesc_addr6: DMAC_FDESC_ADDR

0x2ac - DMAC Former Descriptor Address Register

§dmac_pkg_num6: DMAC_PKG_NUM

0x2b0 - DMAC Package Number Register

§dmac_en7: DMAC_EN

0x2c0 - DMAC Channel Enable Register

§dmac_pau7: DMAC_PAU

0x2c4 - DMAC Channel Pause Register

§dmac_desc_addr7: DMAC_DESC_ADDR

0x2c8 - DMAC Channel Start Address Register

§dmac_cfg7: DMAC_CFG

0x2cc - DMAC Channel Configuration Register

§dmac_cur_src7: DMAC_CUR_SRC

0x2d0 - DMAC Channel Current Source Register

§dmac_cur_dest7: DMAC_CUR_DEST

0x2d4 - DMAC Channel Current Destination Register

§dmac_bcnt_left7: DMAC_BCNT_LEFT

0x2d8 - DMAC Channel Byte Counter Left Register

§dmac_para7: DMAC_PARA

0x2dc - DMAC Channel Parameter Register

§dmac_mode7: DMAC_MODE

0x2e8 - DMAC Mode Register

§dmac_fdesc_addr7: DMAC_FDESC_ADDR

0x2ec - DMAC Former Descriptor Address Register

§dmac_pkg_num7: DMAC_PKG_NUM

0x2f0 - DMAC Package Number Register

§dmac_en8: DMAC_EN

0x300 - DMAC Channel Enable Register

§dmac_pau8: DMAC_PAU

0x304 - DMAC Channel Pause Register

§dmac_desc_addr8: DMAC_DESC_ADDR

0x308 - DMAC Channel Start Address Register

§dmac_cfg8: DMAC_CFG

0x30c - DMAC Channel Configuration Register

§dmac_cur_src8: DMAC_CUR_SRC

0x310 - DMAC Channel Current Source Register

§dmac_cur_dest8: DMAC_CUR_DEST

0x314 - DMAC Channel Current Destination Register

§dmac_bcnt_left8: DMAC_BCNT_LEFT

0x318 - DMAC Channel Byte Counter Left Register

§dmac_para8: DMAC_PARA

0x31c - DMAC Channel Parameter Register

§dmac_mode8: DMAC_MODE

0x328 - DMAC Mode Register

§dmac_fdesc_addr8: DMAC_FDESC_ADDR

0x32c - DMAC Former Descriptor Address Register

§dmac_pkg_num8: DMAC_PKG_NUM

0x330 - DMAC Package Number Register

§dmac_en9: DMAC_EN

0x340 - DMAC Channel Enable Register

§dmac_pau9: DMAC_PAU

0x344 - DMAC Channel Pause Register

§dmac_desc_addr9: DMAC_DESC_ADDR

0x348 - DMAC Channel Start Address Register

§dmac_cfg9: DMAC_CFG

0x34c - DMAC Channel Configuration Register

§dmac_cur_src9: DMAC_CUR_SRC

0x350 - DMAC Channel Current Source Register

§dmac_cur_dest9: DMAC_CUR_DEST

0x354 - DMAC Channel Current Destination Register

§dmac_bcnt_left9: DMAC_BCNT_LEFT

0x358 - DMAC Channel Byte Counter Left Register

§dmac_para9: DMAC_PARA

0x35c - DMAC Channel Parameter Register

§dmac_mode9: DMAC_MODE

0x368 - DMAC Mode Register

§dmac_fdesc_addr9: DMAC_FDESC_ADDR

0x36c - DMAC Former Descriptor Address Register

§dmac_pkg_num9: DMAC_PKG_NUM

0x370 - DMAC Package Number Register

§dmac_en10: DMAC_EN

0x380 - DMAC Channel Enable Register

§dmac_pau10: DMAC_PAU

0x384 - DMAC Channel Pause Register

§dmac_desc_addr10: DMAC_DESC_ADDR

0x388 - DMAC Channel Start Address Register

§dmac_cfg10: DMAC_CFG

0x38c - DMAC Channel Configuration Register

§dmac_cur_src10: DMAC_CUR_SRC

0x390 - DMAC Channel Current Source Register

§dmac_cur_dest10: DMAC_CUR_DEST

0x394 - DMAC Channel Current Destination Register

§dmac_bcnt_left10: DMAC_BCNT_LEFT

0x398 - DMAC Channel Byte Counter Left Register

§dmac_para10: DMAC_PARA

0x39c - DMAC Channel Parameter Register

§dmac_mode10: DMAC_MODE

0x3a8 - DMAC Mode Register

§dmac_fdesc_addr10: DMAC_FDESC_ADDR

0x3ac - DMAC Former Descriptor Address Register

§dmac_pkg_num10: DMAC_PKG_NUM

0x3b0 - DMAC Package Number Register

§dmac_en11: DMAC_EN

0x3c0 - DMAC Channel Enable Register

§dmac_pau11: DMAC_PAU

0x3c4 - DMAC Channel Pause Register

§dmac_desc_addr11: DMAC_DESC_ADDR

0x3c8 - DMAC Channel Start Address Register

§dmac_cfg11: DMAC_CFG

0x3cc - DMAC Channel Configuration Register

§dmac_cur_src11: DMAC_CUR_SRC

0x3d0 - DMAC Channel Current Source Register

§dmac_cur_dest11: DMAC_CUR_DEST

0x3d4 - DMAC Channel Current Destination Register

§dmac_bcnt_left11: DMAC_BCNT_LEFT

0x3d8 - DMAC Channel Byte Counter Left Register

§dmac_para11: DMAC_PARA

0x3dc - DMAC Channel Parameter Register

§dmac_mode11: DMAC_MODE

0x3e8 - DMAC Mode Register

§dmac_fdesc_addr11: DMAC_FDESC_ADDR

0x3ec - DMAC Former Descriptor Address Register

§dmac_pkg_num11: DMAC_PKG_NUM

0x3f0 - DMAC Package Number Register

§dmac_en12: DMAC_EN

0x400 - DMAC Channel Enable Register

§dmac_pau12: DMAC_PAU

0x404 - DMAC Channel Pause Register

§dmac_desc_addr12: DMAC_DESC_ADDR

0x408 - DMAC Channel Start Address Register

§dmac_cfg12: DMAC_CFG

0x40c - DMAC Channel Configuration Register

§dmac_cur_src12: DMAC_CUR_SRC

0x410 - DMAC Channel Current Source Register

§dmac_cur_dest12: DMAC_CUR_DEST

0x414 - DMAC Channel Current Destination Register

§dmac_bcnt_left12: DMAC_BCNT_LEFT

0x418 - DMAC Channel Byte Counter Left Register

§dmac_para12: DMAC_PARA

0x41c - DMAC Channel Parameter Register

§dmac_mode12: DMAC_MODE

0x428 - DMAC Mode Register

§dmac_fdesc_addr12: DMAC_FDESC_ADDR

0x42c - DMAC Former Descriptor Address Register

§dmac_pkg_num12: DMAC_PKG_NUM

0x430 - DMAC Package Number Register

§dmac_en13: DMAC_EN

0x440 - DMAC Channel Enable Register

§dmac_pau13: DMAC_PAU

0x444 - DMAC Channel Pause Register

§dmac_desc_addr13: DMAC_DESC_ADDR

0x448 - DMAC Channel Start Address Register

§dmac_cfg13: DMAC_CFG

0x44c - DMAC Channel Configuration Register

§dmac_cur_src13: DMAC_CUR_SRC

0x450 - DMAC Channel Current Source Register

§dmac_cur_dest13: DMAC_CUR_DEST

0x454 - DMAC Channel Current Destination Register

§dmac_bcnt_left13: DMAC_BCNT_LEFT

0x458 - DMAC Channel Byte Counter Left Register

§dmac_para13: DMAC_PARA

0x45c - DMAC Channel Parameter Register

§dmac_mode13: DMAC_MODE

0x468 - DMAC Mode Register

§dmac_fdesc_addr13: DMAC_FDESC_ADDR

0x46c - DMAC Former Descriptor Address Register

§dmac_pkg_num13: DMAC_PKG_NUM

0x470 - DMAC Package Number Register

§dmac_en14: DMAC_EN

0x480 - DMAC Channel Enable Register

§dmac_pau14: DMAC_PAU

0x484 - DMAC Channel Pause Register

§dmac_desc_addr14: DMAC_DESC_ADDR

0x488 - DMAC Channel Start Address Register

§dmac_cfg14: DMAC_CFG

0x48c - DMAC Channel Configuration Register

§dmac_cur_src14: DMAC_CUR_SRC

0x490 - DMAC Channel Current Source Register

§dmac_cur_dest14: DMAC_CUR_DEST

0x494 - DMAC Channel Current Destination Register

§dmac_bcnt_left14: DMAC_BCNT_LEFT

0x498 - DMAC Channel Byte Counter Left Register

§dmac_para14: DMAC_PARA

0x49c - DMAC Channel Parameter Register

§dmac_mode14: DMAC_MODE

0x4a8 - DMAC Mode Register

§dmac_fdesc_addr14: DMAC_FDESC_ADDR

0x4ac - DMAC Former Descriptor Address Register

§dmac_pkg_num14: DMAC_PKG_NUM

0x4b0 - DMAC Package Number Register

§dmac_en15: DMAC_EN

0x4c0 - DMAC Channel Enable Register

§dmac_pau15: DMAC_PAU

0x4c4 - DMAC Channel Pause Register

§dmac_desc_addr15: DMAC_DESC_ADDR

0x4c8 - DMAC Channel Start Address Register

§dmac_cfg15: DMAC_CFG

0x4cc - DMAC Channel Configuration Register

§dmac_cur_src15: DMAC_CUR_SRC

0x4d0 - DMAC Channel Current Source Register

§dmac_cur_dest15: DMAC_CUR_DEST

0x4d4 - DMAC Channel Current Destination Register

§dmac_bcnt_left15: DMAC_BCNT_LEFT

0x4d8 - DMAC Channel Byte Counter Left Register

§dmac_para15: DMAC_PARA

0x4dc - DMAC Channel Parameter Register

§dmac_mode15: DMAC_MODE

0x4e8 - DMAC Mode Register

§dmac_fdesc_addr15: DMAC_FDESC_ADDR

0x4ec - DMAC Former Descriptor Address Register

§dmac_pkg_num15: DMAC_PKG_NUM

0x4f0 - DMAC Package Number Register

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where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.