Struct d1_pac::emac::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 39 fields
    pub emac_basic_ctl0: EMAC_BASIC_CTL0,
    pub emac_basic_ctl1: EMAC_BASIC_CTL1,
    pub emac_int_sta: EMAC_INT_STA,
    pub emac_int_en: EMAC_INT_EN,
    pub emac_tx_ctl0: EMAC_TX_CTL0,
    pub emac_tx_ctl1: EMAC_TX_CTL1,
    pub emac_tx_flow_ctl: EMAC_TX_FLOW_CTL,
    pub emac_tx_dma_desc_list: EMAC_TX_DMA_DESC_LIST,
    pub emac_rx_ctl0: EMAC_RX_CTL0,
    pub emac_rx_ctl1: EMAC_RX_CTL1,
    pub emac_rx_dma_desc_list: EMAC_RX_DMA_DESC_LIST,
    pub emac_rx_frm_flt: EMAC_RX_FRM_FLT,
    pub emac_rx_hash0: EMAC_RX_HASH0,
    pub emac_rx_hash1: EMAC_RX_HASH1,
    pub emac_mii_cmd: EMAC_MII_CMD,
    pub emac_mii_data: EMAC_MII_DATA,
    pub emac_addr_high0: EMAC_ADDR_HIGH0,
    pub emac_addr_low0: EMAC_ADDR_LOW,
    pub emac_addr_high1: EMAC_ADDR_HIGH,
    pub emac_addr_low1: EMAC_ADDR_LOW,
    pub emac_addr_high2: EMAC_ADDR_HIGH,
    pub emac_addr_low2: EMAC_ADDR_LOW,
    pub emac_addr_high3: EMAC_ADDR_HIGH,
    pub emac_addr_low3: EMAC_ADDR_LOW,
    pub emac_addr_high4: EMAC_ADDR_HIGH,
    pub emac_addr_low4: EMAC_ADDR_LOW,
    pub emac_addr_high5: EMAC_ADDR_HIGH,
    pub emac_addr_low5: EMAC_ADDR_LOW,
    pub emac_addr_high6: EMAC_ADDR_HIGH,
    pub emac_addr_low6: EMAC_ADDR_LOW,
    pub emac_addr_high7: EMAC_ADDR_HIGH,
    pub emac_addr_low7: EMAC_ADDR_LOW,
    pub emac_tx_dma_sta: EMAC_TX_DMA_STA,
    pub emac_tx_cur_desc: EMAC_TX_CUR_DESC,
    pub emac_tx_cur_buf: EMAC_TX_CUR_BUF,
    pub emac_rx_dma_sta: EMAC_RX_DMA_STA,
    pub emac_rx_cur_desc: EMAC_RX_CUR_DESC,
    pub emac_rx_cur_buf: EMAC_RX_CUR_BUF,
    pub emac_rgmii_sta: EMAC_RGMII_STA,
    /* private fields */

}
Expand description

Register block

Fields§

§emac_basic_ctl0: EMAC_BASIC_CTL0

0x00 - EMAC Basic Control Register0

§emac_basic_ctl1: EMAC_BASIC_CTL1

0x04 - EMAC Basic Control Register1

§emac_int_sta: EMAC_INT_STA

0x08 - EMAC Interrupt Status Register

§emac_int_en: EMAC_INT_EN

0x0c - EMAC Interrupt Enable Register

§emac_tx_ctl0: EMAC_TX_CTL0

0x10 - EMAC Transmit Control Register0

§emac_tx_ctl1: EMAC_TX_CTL1

0x14 - EMAC Transmit Control Register1

§emac_tx_flow_ctl: EMAC_TX_FLOW_CTL

0x1c - EMAC Transmit Flow Control Register

§emac_tx_dma_desc_list: EMAC_TX_DMA_DESC_LIST

0x20 - EMAC Transmit Descriptor List Address Register

§emac_rx_ctl0: EMAC_RX_CTL0

0x24 - EMAC Receive Control Register0

§emac_rx_ctl1: EMAC_RX_CTL1

0x28 - EMAC Receive Control Register1

§emac_rx_dma_desc_list: EMAC_RX_DMA_DESC_LIST

0x34 - EMAC Receive Descriptor List Address Register

§emac_rx_frm_flt: EMAC_RX_FRM_FLT

0x38 - EMAC Receive Frame Filter Register

§emac_rx_hash0: EMAC_RX_HASH0

0x40 - EMAC Hash Table Register0

§emac_rx_hash1: EMAC_RX_HASH1

0x44 - EMAC Hash Table Register1

§emac_mii_cmd: EMAC_MII_CMD

0x48 - EMAC Management Interface Command Register

§emac_mii_data: EMAC_MII_DATA

0x4c - EMAC Management Interface Data Register

§emac_addr_high0: EMAC_ADDR_HIGH0

0x50 - EMAC MAC Address High Register

§emac_addr_low0: EMAC_ADDR_LOW

0x54 - EMAC MAC Address Low Register

§emac_addr_high1: EMAC_ADDR_HIGH

0x58 - EMAC MAC Address High Register

§emac_addr_low1: EMAC_ADDR_LOW

0x5c - EMAC MAC Address Low Register

§emac_addr_high2: EMAC_ADDR_HIGH

0x60 - EMAC MAC Address High Register

§emac_addr_low2: EMAC_ADDR_LOW

0x64 - EMAC MAC Address Low Register

§emac_addr_high3: EMAC_ADDR_HIGH

0x68 - EMAC MAC Address High Register

§emac_addr_low3: EMAC_ADDR_LOW

0x6c - EMAC MAC Address Low Register

§emac_addr_high4: EMAC_ADDR_HIGH

0x70 - EMAC MAC Address High Register

§emac_addr_low4: EMAC_ADDR_LOW

0x74 - EMAC MAC Address Low Register

§emac_addr_high5: EMAC_ADDR_HIGH

0x78 - EMAC MAC Address High Register

§emac_addr_low5: EMAC_ADDR_LOW

0x7c - EMAC MAC Address Low Register

§emac_addr_high6: EMAC_ADDR_HIGH

0x80 - EMAC MAC Address High Register

§emac_addr_low6: EMAC_ADDR_LOW

0x84 - EMAC MAC Address Low Register

§emac_addr_high7: EMAC_ADDR_HIGH

0x88 - EMAC MAC Address High Register

§emac_addr_low7: EMAC_ADDR_LOW

0x8c - EMAC MAC Address Low Register

§emac_tx_dma_sta: EMAC_TX_DMA_STA

0xb0 - EMAC Transmit DMA Status Register

§emac_tx_cur_desc: EMAC_TX_CUR_DESC

0xb4 - EMAC Current Transmit Descriptor Register

§emac_tx_cur_buf: EMAC_TX_CUR_BUF

0xb8 - EMAC Current Transmit Buffer Address Register

§emac_rx_dma_sta: EMAC_RX_DMA_STA

0xc0 - EMAC Receive DMA Status Register

§emac_rx_cur_desc: EMAC_RX_CUR_DESC

0xc4 - EMAC Current Receive Descriptor Register

§emac_rx_cur_buf: EMAC_RX_CUR_BUF

0xc8 - EMAC Current Receive Buffer Address Register

§emac_rgmii_sta: EMAC_RGMII_STA

0xd0 - EMAC RGMII Status Register

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