Struct d1_pac::gpio::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 76 fields
    pub pb_cfg0: PB_CFG0,
    pub pb_cfg1: PB_CFG1,
    pub pb_dat: PB_DAT,
    pub pb_drv0: PB_DRV0,
    pub pb_drv1: PB_DRV1,
    pub pb_pull0: PB_PULL0,
    pub pc_cfg0: PC_CFG0,
    pub pc_dat: PC_DAT,
    pub pc_drv0: PC_DRV0,
    pub pc_pull0: PC_PULL0,
    pub pd_cfg0: PD_CFG0,
    pub pd_cfg1: PD_CFG1,
    pub pd_cfg2: PD_CFG2,
    pub pd_dat: PD_DAT,
    pub pd_drv0: PD_DRV0,
    pub pd_drv1: PD_DRV1,
    pub pd_drv2: PD_DRV2,
    pub pd_pull0: PD_PULL0,
    pub pd_pull1: PD_PULL1,
    pub pe_cfg0: PE_CFG0,
    pub pe_cfg1: PE_CFG1,
    pub pe_cfg2: PE_CFG2,
    pub pe_dat: PE_DAT,
    pub pe_drv0: PE_DRV0,
    pub pe_drv1: PE_DRV1,
    pub pe_drv2: PE_DRV2,
    pub pe_pull0: PE_PULL0,
    pub pe_pull1: PE_PULL1,
    pub pf_cfg0: PF_CFG0,
    pub pf_dat: PF_DAT,
    pub pf_drv0: PF_DRV0,
    pub pf_pull0: PF_PULL0,
    pub pg_cfg0: PG_CFG0,
    pub pg_cfg1: PG_CFG1,
    pub pg_cfg2: PG_CFG2,
    pub pg_dat: PG_DAT,
    pub pg_drv0: PG_DRV0,
    pub pg_drv1: PG_DRV1,
    pub pg_drv2: PG_DRV2,
    pub pg_pull0: PG_PULL0,
    pub pg_pull1: PG_PULL1,
    pub pb_eint_cfg0: PB_EINT_CFG0,
    pub pb_eint_cfg1: PB_EINT_CFG1,
    pub pb_eint_ctl: PB_EINT_CTL,
    pub pb_eint_status: PB_EINT_STATUS,
    pub pb_eint_deb: PB_EINT_DEB,
    pub pc_eint_cfg0: PC_EINT_CFG0,
    pub pc_eint_ctl: PC_EINT_CTL,
    pub pc_eint_status: PC_EINT_STATUS,
    pub pc_eint_deb: PC_EINT_DEB,
    pub pd_eint_cfg0: PD_EINT_CFG0,
    pub pd_eint_cfg1: PD_EINT_CFG1,
    pub pd_eint_cfg2: PD_EINT_CFG2,
    pub pd_eint_ctl: PD_EINT_CTL,
    pub pd_eint_status: PD_EINT_STATUS,
    pub pd_eint_deb: PD_EINT_DEB,
    pub pe_eint_cfg0: PE_EINT_CFG0,
    pub pe_eint_cfg1: PE_EINT_CFG1,
    pub pe_eint_cfg2: PE_EINT_CFG2,
    pub pe_eint_ctl: PE_EINT_CTL,
    pub pe_eint_status: PE_EINT_STATUS,
    pub pe_eint_deb: PE_EINT_DEB,
    pub pf_eint_cfg0: PF_EINT_CFG0,
    pub pf_eint_ctl: PF_EINT_CTL,
    pub pf_eint_status: PF_EINT_STATUS,
    pub pf_eint_deb: PF_EINT_DEB,
    pub pg_eint_cfg0: PG_EINT_CFG0,
    pub pg_eint_cfg1: PG_EINT_CFG1,
    pub pg_eint_cfg2: PG_EINT_CFG2,
    pub pg_eint_ctl: PG_EINT_CTL,
    pub pg_eint_status: PG_EINT_STATUS,
    pub pg_eint_deb: PG_EINT_DEB,
    pub pio_pow_mod_sel: PIO_POW_MOD_SEL,
    pub pio_pow_ms_ctl: PIO_POW_MS_CTL,
    pub pio_pow_val: PIO_POW_VAL,
    pub pio_pow_vol_sel_ctl: PIO_POW_VOL_SEL_CTL,
    /* private fields */

}
Expand description

Register block

Fields§

§pb_cfg0: PB_CFG0

0x30 - PB Configure Register 0

§pb_cfg1: PB_CFG1

0x34 - PB Configure Register 1

§pb_dat: PB_DAT

0x40 - PB Data Register

§pb_drv0: PB_DRV0

0x44 - PB Multi_Driving Register 0

§pb_drv1: PB_DRV1

0x48 - PB Multi_Driving Register 1

§pb_pull0: PB_PULL0

0x54 - PB Pull Register 0

§pc_cfg0: PC_CFG0

0x60 - PC Configure Register 0

§pc_dat: PC_DAT

0x70 - PC Data Register

§pc_drv0: PC_DRV0

0x74 - PC Multi_Driving Register 0

§pc_pull0: PC_PULL0

0x84 - PC Pull Register 0

§pd_cfg0: PD_CFG0

0x90 - PD Configure Register 0

§pd_cfg1: PD_CFG1

0x94 - PD Configure Register 1

§pd_cfg2: PD_CFG2

0x98 - PD Configure Register 2

§pd_dat: PD_DAT

0xa0 - PD Data Register

§pd_drv0: PD_DRV0

0xa4 - PD Multi_Driving Register 0

§pd_drv1: PD_DRV1

0xa8 - PD Multi_Driving Register 1

§pd_drv2: PD_DRV2

0xac - PD Multi_Driving Register 2

§pd_pull0: PD_PULL0

0xb4 - PD Pull Register 0

§pd_pull1: PD_PULL1

0xb8 - PD Pull Register 1

§pe_cfg0: PE_CFG0

0xc0 - PE Configure Register 0

§pe_cfg1: PE_CFG1

0xc4 - PE Configure Register 1

§pe_cfg2: PE_CFG2

0xc8 - PE Configure Register 2

§pe_dat: PE_DAT

0xd0 - PE Data Register

§pe_drv0: PE_DRV0

0xd4 - PE Multi_Driving Register 0

§pe_drv1: PE_DRV1

0xd8 - PE Multi_Driving Register 1

§pe_drv2: PE_DRV2

0xdc - PE Multi_Driving Register 2

§pe_pull0: PE_PULL0

0xe4 - PE Pull Register 0

§pe_pull1: PE_PULL1

0xe8 - PE Pull Register 1

§pf_cfg0: PF_CFG0

0xf0 - PF Configure Register 0

§pf_dat: PF_DAT

0x100 - PF Data Register

§pf_drv0: PF_DRV0

0x104 - PF Multi_Driving Register 0

§pf_pull0: PF_PULL0

0x114 - PF Pull Register 0

§pg_cfg0: PG_CFG0

0x120 - PG Configure Register 0

§pg_cfg1: PG_CFG1

0x124 - PG Configure Register 1

§pg_cfg2: PG_CFG2

0x128 - PG Configure Register 2

§pg_dat: PG_DAT

0x130 - PG Data Register

§pg_drv0: PG_DRV0

0x134 - PG Multi_Driving Register 0

§pg_drv1: PG_DRV1

0x138 - PG Multi_Driving Register 1

§pg_drv2: PG_DRV2

0x13c - PG Multi_Driving Register 2

§pg_pull0: PG_PULL0

0x144 - PG Pull Register 0

§pg_pull1: PG_PULL1

0x148 - PG Pull Register 1

§pb_eint_cfg0: PB_EINT_CFG0

0x220 - PB External Interrupt Configure Register 0

§pb_eint_cfg1: PB_EINT_CFG1

0x224 - PB External Interrupt Configure Register 1

§pb_eint_ctl: PB_EINT_CTL

0x230 - PB External Interrupt Control Register

§pb_eint_status: PB_EINT_STATUS

0x234 - PB External Interrupt Status Register

§pb_eint_deb: PB_EINT_DEB

0x238 - PB External Interrupt Debounce Register

§pc_eint_cfg0: PC_EINT_CFG0

0x240 - PC External Interrupt Configure Register 0

§pc_eint_ctl: PC_EINT_CTL

0x250 - PC External Interrupt Control Register

§pc_eint_status: PC_EINT_STATUS

0x254 - PC External Interrupt Status Register

§pc_eint_deb: PC_EINT_DEB

0x258 - PC External Interrupt Debounce Register

§pd_eint_cfg0: PD_EINT_CFG0

0x260 - PD External Interrupt Configure Register 0

§pd_eint_cfg1: PD_EINT_CFG1

0x264 - PD External Interrupt Configure Register 1

§pd_eint_cfg2: PD_EINT_CFG2

0x268 - PD External Interrupt Configure Register 2

§pd_eint_ctl: PD_EINT_CTL

0x270 - PD External Interrupt Control Register

§pd_eint_status: PD_EINT_STATUS

0x274 - PD External Interrupt Status Register

§pd_eint_deb: PD_EINT_DEB

0x278 - PD External Interrupt Debounce Register

§pe_eint_cfg0: PE_EINT_CFG0

0x280 - PE External Interrupt Configure Register 0

§pe_eint_cfg1: PE_EINT_CFG1

0x284 - PE External Interrupt Configure Register 1

§pe_eint_cfg2: PE_EINT_CFG2

0x288 - PE External Interrupt Configure Register 2

§pe_eint_ctl: PE_EINT_CTL

0x290 - PE External Interrupt Control Register

§pe_eint_status: PE_EINT_STATUS

0x294 - PE External Interrupt Status Register

§pe_eint_deb: PE_EINT_DEB

0x298 - PE External Interrupt Debounce Register

§pf_eint_cfg0: PF_EINT_CFG0

0x2a0 - PF External Interrupt Configure Register 0

§pf_eint_ctl: PF_EINT_CTL

0x2b0 - PF External Interrupt Control Register

§pf_eint_status: PF_EINT_STATUS

0x2b4 - PF External Interrupt Status Register

§pf_eint_deb: PF_EINT_DEB

0x2b8 - PF External Interrupt Debounce Register

§pg_eint_cfg0: PG_EINT_CFG0

0x2c0 - PG External Interrupt Configure Register 0

§pg_eint_cfg1: PG_EINT_CFG1

0x2c4 - PG External Interrupt Configure Register 1

§pg_eint_cfg2: PG_EINT_CFG2

0x2c8 - PG External Interrupt Configure Register 2

§pg_eint_ctl: PG_EINT_CTL

0x2d0 - PG External Interrupt Control Register

§pg_eint_status: PG_EINT_STATUS

0x2d4 - PG External Interrupt Status Register

§pg_eint_deb: PG_EINT_DEB

0x2d8 - PG External Interrupt Debounce Register

§pio_pow_mod_sel: PIO_POW_MOD_SEL

0x340 - PIO Group Withstand Voltage Mode Select Register

§pio_pow_ms_ctl: PIO_POW_MS_CTL

0x344 - PIO Group Withstand Voltage Mode Select Control Register

§pio_pow_val: PIO_POW_VAL

0x348 - PIO Group Power Value Register

§pio_pow_vol_sel_ctl: PIO_POW_VOL_SEL_CTL

0x350 - PIO Group Power Voltage Select Control Register

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