Struct d1_pac::i2s_pcm::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 39 fields
    pub i2s_pcm_ctl: I2S_PCM_CTL,
    pub i2s_pcm_fmt0: I2S_PCM_FMT0,
    pub i2s_pcm_fmt1: I2S_PCM_FMT1,
    pub i2s_pcm_ista: I2S_PCM_ISTA,
    pub i2s_pcm_rxfifo: I2S_PCM_RXFIFO,
    pub i2s_pcm_fctl: I2S_PCM_FCTL,
    pub i2s_pcm_fsta: I2S_PCM_FSTA,
    pub i2s_pcm_int: I2S_PCM_INT,
    pub i2s_pcm_txfifo: I2S_PCM_TXFIFO,
    pub i2s_pcm_clkd: I2S_PCM_CLKD,
    pub i2s_pcm_txcnt: I2S_PCM_TXCNT,
    pub i2s_pcm_rxcnt: I2S_PCM_RXCNT,
    pub i2s_pcm_chcfg: I2S_PCM_CHCFG,
    pub i2s_pcm_tx0chsel: I2S_PCM_TX0CHSEL,
    pub i2s_pcm_tx1chsel: I2S_PCM_TX1CHSEL,
    pub i2s_pcm_tx2chsel: I2S_PCM_TX2CHSEL,
    pub i2s_pcm_tx3chsel: I2S_PCM_TX3CHSEL,
    pub i2s_pcm_tx0chmap0: I2S_PCM_TX0CHMAP0,
    pub i2s_pcm_tx0chmap1: I2S_PCM_TX0CHMAP1,
    pub i2s_pcm_tx1chmap0: I2S_PCM_TX1CHMAP0,
    pub i2s_pcm_tx1chmap1: I2S_PCM_TX1CHMAP1,
    pub i2s_pcm_tx2chmap0: I2S_PCM_TX2CHMAP0,
    pub i2s_pcm_tx2chmap1: I2S_PCM_TX2CHMAP1,
    pub i2s_pcm_tx3chmap0: I2S_PCM_TX3CHMAP0,
    pub i2s_pcm_tx3chmap1: I2S_PCM_TX3CHMAP1,
    pub i2s_pcm_rxchsel: I2S_PCM_RXCHSEL,
    pub i2s_pcm_rxchmap0: I2S_PCM_RXCHMAP0,
    pub i2s_pcm_rxchmap1: I2S_PCM_RXCHMAP1,
    pub i2s_pcm_rxchmap2: I2S_PCM_RXCHMAP2,
    pub i2s_pcm_rxchmap3: I2S_PCM_RXCHMAP3,
    pub mclkcfg: MCLKCFG,
    pub fsout_cfg: FSOUT_CFG,
    pub fsin_extcfg: FSIN_EXTCFG,
    pub asrcen: ASRCEN,
    pub asrcmancfg: ASRCMANCFG,
    pub asrcratiostat: ASRCRATIOSTAT,
    pub asrcfifostat: ASRCFIFOSTAT,
    pub asrcmbistcfg: ASRCMBISTCFG,
    pub asrcmbiststat: ASRCMBISTSTAT,
    /* private fields */

}
Expand description

Register block

Fields§

§i2s_pcm_ctl: I2S_PCM_CTL

0x00 - I2S/PCM Control Register

§i2s_pcm_fmt0: I2S_PCM_FMT0

0x04 - I2S/PCM Format Register 0

§i2s_pcm_fmt1: I2S_PCM_FMT1

0x08 - I2S/PCM Format Register 1

§i2s_pcm_ista: I2S_PCM_ISTA

0x0c - I2S/PCM Interrupt Status Register

§i2s_pcm_rxfifo: I2S_PCM_RXFIFO

0x10 - I2S/PCM RXFIFO Register

§i2s_pcm_fctl: I2S_PCM_FCTL

0x14 - I2S/PCM FIFO Control Register

§i2s_pcm_fsta: I2S_PCM_FSTA

0x18 - I2S/PCM FIFO Status Register

§i2s_pcm_int: I2S_PCM_INT

0x1c - I2S/PCM DMA and Interrupt Control Register

§i2s_pcm_txfifo: I2S_PCM_TXFIFO

0x20 - I2S/PCM TXFIFO Register

§i2s_pcm_clkd: I2S_PCM_CLKD

0x24 - I2S/PCM Clock Divide Register

§i2s_pcm_txcnt: I2S_PCM_TXCNT

0x28 - I2S/PCM TX Sample Counter Register

§i2s_pcm_rxcnt: I2S_PCM_RXCNT

0x2c - I2S/PCM RX Sample Counter Register

§i2s_pcm_chcfg: I2S_PCM_CHCFG

0x30 - I2S/PCM Channel Configuration Register

§i2s_pcm_tx0chsel: I2S_PCM_TX0CHSEL

0x34 - I2S/PCM TX0 Channel Select Register

§i2s_pcm_tx1chsel: I2S_PCM_TX1CHSEL

0x38 - I2S/PCM TX1 Channel Select Register

§i2s_pcm_tx2chsel: I2S_PCM_TX2CHSEL

0x3c - I2S/PCM TX2 Channel Select Register

§i2s_pcm_tx3chsel: I2S_PCM_TX3CHSEL

0x40 - I2S/PCM TX3 Channel Select Register

§i2s_pcm_tx0chmap0: I2S_PCM_TX0CHMAP0

0x44 - I2S/PCM TX0 Channel Mapping Register0

§i2s_pcm_tx0chmap1: I2S_PCM_TX0CHMAP1

0x48 - I2S/PCM TX0 Channel Mapping Register1

§i2s_pcm_tx1chmap0: I2S_PCM_TX1CHMAP0

0x4c - I2S/PCM TX1 Channel Mapping Register0

§i2s_pcm_tx1chmap1: I2S_PCM_TX1CHMAP1

0x50 - I2S/PCM TX1 Channel Mapping Register1

§i2s_pcm_tx2chmap0: I2S_PCM_TX2CHMAP0

0x54 - I2S/PCM TX2 Channel Mapping Register0

§i2s_pcm_tx2chmap1: I2S_PCM_TX2CHMAP1

0x58 - I2S/PCM TX2 Channel Mapping Register1

§i2s_pcm_tx3chmap0: I2S_PCM_TX3CHMAP0

0x5c - I2S/PCM TX3 Channel Mapping Register0

§i2s_pcm_tx3chmap1: I2S_PCM_TX3CHMAP1

0x60 - I2S/PCM TX3 Channel Mapping Register1

§i2s_pcm_rxchsel: I2S_PCM_RXCHSEL

0x64 - I2S/PCM RX Channel Select Register

§i2s_pcm_rxchmap0: I2S_PCM_RXCHMAP0

0x68 - I2S/PCM RX Channel Mapping Register0

§i2s_pcm_rxchmap1: I2S_PCM_RXCHMAP1

0x6c - I2S/PCM RX Channel Mapping Register1

§i2s_pcm_rxchmap2: I2S_PCM_RXCHMAP2

0x70 - I2S/PCM RX Channel Mapping Register2

§i2s_pcm_rxchmap3: I2S_PCM_RXCHMAP3

0x74 - I2S/PCM RX Channel Mapping Register3

§mclkcfg: MCLKCFG

0x80 - ASRC MCLK Configuration Register

§fsout_cfg: FSOUT_CFG

0x84 - ASRC Out Sample Rate Configuration Register

§fsin_extcfg: FSIN_EXTCFG

0x88 - ASRC Input Sample Pulse Extend Configuration Register

§asrcen: ASRCEN

0x8c - ASRC Enable Register

§asrcmancfg: ASRCMANCFG

0x90 - ASRC Manual Ratio Configuration Register

§asrcratiostat: ASRCRATIOSTAT

0x94 - ASRC Status Register

§asrcfifostat: ASRCFIFOSTAT

0x98 - ASRC FIFO Level Status Register

§asrcmbistcfg: ASRCMBISTCFG

0x9c - ASRC MBIST Test Configuration Register

§asrcmbiststat: ASRCMBISTSTAT

0xa0 - ASRC MBIST Test Status Register

Auto Trait Implementations§

Blanket Implementations§

source§

impl<T> Any for T
where T: 'static + ?Sized,

source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
source§

impl<T> Borrow<T> for T
where T: ?Sized,

source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
source§

impl<T> From<T> for T

source§

fn from(t: T) -> T

Returns the argument unchanged.

source§

impl<T, U> Into<U> for T
where U: From<T>,

source§

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

source§

impl<T, U> TryFrom<U> for T
where U: Into<T>,

§

type Error = Infallible

The type returned in the event of a conversion error.
source§

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
source§

impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

§

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
source§

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.