Struct d1_pac::iommu::iommu_reset::R
source · pub struct R(/* private fields */);Expand description
Register iommu_reset reader
Implementations§
source§impl R
impl R
sourcepub unsafe fn m_rst(&self, n: u8) -> M_RST_R
pub unsafe fn m_rst(&self, n: u8) -> M_RST_R
Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m0_rst(&self) -> M_RST_R
pub fn m0_rst(&self) -> M_RST_R
Bit 0 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m1_rst(&self) -> M_RST_R
pub fn m1_rst(&self) -> M_RST_R
Bit 1 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m2_rst(&self) -> M_RST_R
pub fn m2_rst(&self) -> M_RST_R
Bit 2 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m3_rst(&self) -> M_RST_R
pub fn m3_rst(&self) -> M_RST_R
Bit 3 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m4_rst(&self) -> M_RST_R
pub fn m4_rst(&self) -> M_RST_R
Bit 4 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m5_rst(&self) -> M_RST_R
pub fn m5_rst(&self) -> M_RST_R
Bit 5 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m6_rst(&self) -> M_RST_R
pub fn m6_rst(&self) -> M_RST_R
Bit 6 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn mtlb_rst(&self) -> MTLB_RST_R
pub fn mtlb_rst(&self) -> MTLB_RST_R
Bit 16 - Macrotlb Reset
Macro TLB address convert lane software reset switch.
When PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn pc_rst(&self) -> PC_RST_R
pub fn pc_rst(&self) -> PC_RST_R
Bit 17 - PTW Cache Reset
PTW Cache address convert lane software reset switch.
When PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn iommu_reset(&self) -> IOMMU_RESET_R
pub fn iommu_reset(&self) -> IOMMU_RESET_R
Bit 31 - IOMMU Software Reset Switch、n Before IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset.