Struct d1_pac::iommu::iommu_reset::W
source · pub struct W(/* private fields */);Expand description
Register iommu_reset writer
Implementations§
source§impl W
impl W
sourcepub unsafe fn m_rst<const O: u8>(&mut self) -> M_RST_W<'_, O>
pub unsafe fn m_rst<const O: u8>(&mut self) -> M_RST_W<'_, O>
Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m0_rst(&mut self) -> M_RST_W<'_, 0>
pub fn m0_rst(&mut self) -> M_RST_W<'_, 0>
Bit 0 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m1_rst(&mut self) -> M_RST_W<'_, 1>
pub fn m1_rst(&mut self) -> M_RST_W<'_, 1>
Bit 1 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m2_rst(&mut self) -> M_RST_W<'_, 2>
pub fn m2_rst(&mut self) -> M_RST_W<'_, 2>
Bit 2 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m3_rst(&mut self) -> M_RST_W<'_, 3>
pub fn m3_rst(&mut self) -> M_RST_W<'_, 3>
Bit 3 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m4_rst(&mut self) -> M_RST_W<'_, 4>
pub fn m4_rst(&mut self) -> M_RST_W<'_, 4>
Bit 4 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m5_rst(&mut self) -> M_RST_W<'_, 5>
pub fn m5_rst(&mut self) -> M_RST_W<'_, 5>
Bit 5 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn m6_rst(&mut self) -> M_RST_W<'_, 6>
pub fn m6_rst(&mut self) -> M_RST_W<'_, 6>
Bit 6 - Master[i] Reset
Master[i] address convert lane software reset switch.
When Master[i] occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn mtlb_rst(&mut self) -> MTLB_RST_W<'_, 16>
pub fn mtlb_rst(&mut self) -> MTLB_RST_W<'_, 16>
Bit 16 - Macrotlb Reset
Macro TLB address convert lane software reset switch.
When PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn pc_rst(&mut self) -> PC_RST_W<'_, 17>
pub fn pc_rst(&mut self) -> PC_RST_W<'_, 17>
Bit 17 - PTW Cache Reset
PTW Cache address convert lane software reset switch.
When PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually.
sourcepub fn iommu_reset(&mut self) -> IOMMU_RESET_W<'_, 31>
pub fn iommu_reset(&mut self) -> IOMMU_RESET_W<'_, 31>
Bit 31 - IOMMU Software Reset Switch、n Before IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset.