Struct d1_pac::iommu::iommu_tlb_prefetch::R

pub struct R(/* private fields */);

Register iommu_tlb_prefetch reader

Implementations

impl R

pub unsafe fn mi_tlb_pf(&self, n: u8) -> MI_TLB_PF_R

Micro TLB6 prefetch enable

pub fn mi_tlb0_pf(&self) -> MI_TLB_PF_R

Bit 0 - Micro TLB6 prefetch enable

pub fn mi_tlb1_pf(&self) -> MI_TLB_PF_R

Bit 1 - Micro TLB6 prefetch enable

pub fn mi_tlb2_pf(&self) -> MI_TLB_PF_R

Bit 2 - Micro TLB6 prefetch enable

pub fn mi_tlb3_pf(&self) -> MI_TLB_PF_R

Bit 3 - Micro TLB6 prefetch enable

pub fn mi_tlb4_pf(&self) -> MI_TLB_PF_R

Bit 4 - Micro TLB6 prefetch enable

pub fn mi_tlb5_pf(&self) -> MI_TLB_PF_R

Bit 5 - Micro TLB6 prefetch enable

pub fn mi_tlb6_pf(&self) -> MI_TLB_PF_R

Bit 6 - Micro TLB6 prefetch enable

pub fn pf_vl_pt_to_mt(&self) -> PF_VL_PT_TO_MT_R

Bit 16 - Prefetch Value Pagetable to Macro TLB

If the function is enabled, the prefetch function will not update the invalid Level2 page table to Macro TLB.

pub fn pf_vl_pt_to_pc(&self) -> PF_VL_PT_TO_PC_R

Bit 17 - Prefetch Value Pagetable to PTW Cache

If the function is enabled, the prefetch function will not update the invalid Level1 page table to PTW cache.

Methods from Deref<Target = R<IOMMU_TLB_PREFETCH_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<IOMMU_TLB_PREFETCH_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<IOMMU_TLB_PREFETCH_SPEC>> for R

fn from(reader: R<IOMMU_TLB_PREFETCH_SPEC>) -> Self

Converts to this type from the input type.