Struct d1_pac::iommu::iommu_tlb_prefetch::W

pub struct W(/* private fields */);

Register iommu_tlb_prefetch writer

Implementations

impl W

pub unsafe fn mi_tlb_pf<const O: u8>(&mut self) -> MI_TLB_PF_W<'_, O>

Micro TLB6 prefetch enable

pub fn mi_tlb0_pf(&mut self) -> MI_TLB_PF_W<'_, 0>

Bit 0 - Micro TLB6 prefetch enable

pub fn mi_tlb1_pf(&mut self) -> MI_TLB_PF_W<'_, 1>

Bit 1 - Micro TLB6 prefetch enable

pub fn mi_tlb2_pf(&mut self) -> MI_TLB_PF_W<'_, 2>

Bit 2 - Micro TLB6 prefetch enable

pub fn mi_tlb3_pf(&mut self) -> MI_TLB_PF_W<'_, 3>

Bit 3 - Micro TLB6 prefetch enable

pub fn mi_tlb4_pf(&mut self) -> MI_TLB_PF_W<'_, 4>

Bit 4 - Micro TLB6 prefetch enable

pub fn mi_tlb5_pf(&mut self) -> MI_TLB_PF_W<'_, 5>

Bit 5 - Micro TLB6 prefetch enable

pub fn mi_tlb6_pf(&mut self) -> MI_TLB_PF_W<'_, 6>

Bit 6 - Micro TLB6 prefetch enable

pub fn pf_vl_pt_to_mt(&mut self) -> PF_VL_PT_TO_MT_W<'_, 16>

Bit 16 - Prefetch Value Pagetable to Macro TLB

If the function is enabled, the prefetch function will not update the invalid Level2 page table to Macro TLB.

pub fn pf_vl_pt_to_pc(&mut self) -> PF_VL_PT_TO_PC_W<'_, 17>

Bit 17 - Prefetch Value Pagetable to PTW Cache

If the function is enabled, the prefetch function will not update the invalid Level1 page table to PTW cache.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<IOMMU_TLB_PREFETCH_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<IOMMU_TLB_PREFETCH_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<IOMMU_TLB_PREFETCH_SPEC>> for W

fn from(writer: W<IOMMU_TLB_PREFETCH_SPEC>) -> Self

Converts to this type from the input type.