Struct d1_pac::pwm::pisr::R

pub struct R(/* private fields */);

Register pisr reader

Implementations

impl R

pub unsafe fn pis(&self, n: u8) -> PIS_R

PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis0(&self) -> PIS_R

Bit 0 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis1(&self) -> PIS_R

Bit 1 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis2(&self) -> PIS_R

Bit 2 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis3(&self) -> PIS_R

Bit 3 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis4(&self) -> PIS_R

Bit 4 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis5(&self) -> PIS_R

Bit 5 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis6(&self) -> PIS_R

Bit 6 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis7(&self) -> PIS_R

Bit 7 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub unsafe fn pgis(&self, n: u8) -> PGIS_R

PWM Group Interrupt Status

pub fn pgis0(&self) -> PGIS_R

Bit 16 - PWM Group Interrupt Status

pub fn pgis1(&self) -> PGIS_R

Bit 17 - PWM Group Interrupt Status

pub fn pgis2(&self) -> PGIS_R

Bit 18 - PWM Group Interrupt Status

pub fn pgis3(&self) -> PGIS_R

Bit 19 - PWM Group Interrupt Status

Methods from Deref<Target = R<PISR_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<PISR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<PISR_SPEC>> for R

fn from(reader: R<PISR_SPEC>) -> Self

Converts to this type from the input type.