Struct d1_pac::pwm::pisr::W

pub struct W(/* private fields */);

Register pisr writer

Implementations

impl W

pub unsafe fn pis<const O: u8>(&mut self) -> PIS_W<'_, O>

PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis0(&mut self) -> PIS_W<'_, 0>

Bit 0 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis1(&mut self) -> PIS_W<'_, 1>

Bit 1 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis2(&mut self) -> PIS_W<'_, 2>

Bit 2 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis3(&mut self) -> PIS_W<'_, 3>

Bit 3 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis4(&mut self) -> PIS_W<'_, 4>

Bit 4 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis5(&mut self) -> PIS_W<'_, 5>

Bit 5 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis6(&mut self) -> PIS_W<'_, 6>

Bit 6 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub fn pis7(&mut self) -> PIS_W<'_, 7>

Bit 7 - PWM Channel Interrupt Status

When the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.

Reads 0: PWM channel 0 interrupt is not pending.

Reads 1: PWM channel 0 interrupt is pending.

Writes 0: No effect.

Writes 1: Clear PWM channel 0 interrupt status.

pub unsafe fn pgis<const O: u8>(&mut self) -> PGIS_W<'_, O>

PWM Group Interrupt Status

pub fn pgis0(&mut self) -> PGIS_W<'_, 16>

Bit 16 - PWM Group Interrupt Status

pub fn pgis1(&mut self) -> PGIS_W<'_, 17>

Bit 17 - PWM Group Interrupt Status

pub fn pgis2(&mut self) -> PGIS_W<'_, 18>

Bit 18 - PWM Group Interrupt Status

pub fn pgis3(&mut self) -> PGIS_W<'_, 19>

Bit 19 - PWM Group Interrupt Status

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<PISR_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<PISR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<PISR_SPEC>> for W

fn from(writer: W<PISR_SPEC>) -> Self

Converts to this type from the input type.