pub struct R(/* private fields */);
Expand description
Register dcxo_ctrl
reader
Implementations§
source§impl R
impl R
sourcepub fn clk16m_rc_en(&self) -> CLK16M_RC_EN_R
pub fn clk16m_rc_en(&self) -> CLK16M_RC_EN_R
Bit 0 - The related register configuration is necessary to ensure the reset debounce circuit has a stable clock source. The first time SoC starts up, by default, the reset debounce circuit of SoC uses 32K divided by RC16M. In power-off, software reads the related bit to ensure whether EXT32K is working normally, if it is normal, first switch the clock source of debounce circuit to EXT32K, then close RC16M. Without EXT32K scenario or external RTC scenario, software confirms firstly whether EXT32K is working normally before switching, or software does not close RC16M.
sourcepub fn rsto_dly_sel(&self) -> RSTO_DLY_SEL_R
pub fn rsto_dly_sel(&self) -> RSTO_DLY_SEL_R
Bit 2 - For Debug Use Only.
It cannot configure to 0 in normal state.
sourcepub fn dcxo_rfclk_enhance(&self) -> DCXO_RFCLK_ENHANCE_R
pub fn dcxo_rfclk_enhance(&self) -> DCXO_RFCLK_ENHANCE_R
Bits 4:5 - DCXO rfclk enhance
Enhance driving capacity of output OUT_RF_REFCLK, 0x0 for 5 pF, 0x1 for 10 pF, 0x2 for 15 pF, 0x3 for 20 pF.
sourcepub fn xtal_mode(&self) -> XTAL_MODE_R
pub fn xtal_mode(&self) -> XTAL_MODE_R
Bit 6 - Xtal mode enable signal, active high
sourcepub fn dcxo_ldo_inrushb(&self) -> DCXO_LDO_INRUSHB_R
pub fn dcxo_ldo_inrushb(&self) -> DCXO_LDO_INRUSHB_R
Bit 7 - DCXO LDO driving capacity signal, active high
sourcepub fn dcxo_trim(&self) -> DCXO_TRIM_R
pub fn dcxo_trim(&self) -> DCXO_TRIM_R
Bits 16:22 - DCXO cap array value
The capacity cell is 55 fF.
sourcepub fn dcxo_ictrl(&self) -> DCXO_ICTRL_R
pub fn dcxo_ictrl(&self) -> DCXO_ICTRL_R
Bits 24:27 - DCXO current control value
sourcepub fn clk_req_enb(&self) -> CLK_REQ_ENB_R
pub fn clk_req_enb(&self) -> CLK_REQ_ENB_R
Bit 31 - Clock REQ enable