Struct d1_pac::smhc::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 40 fields
    pub smhc_ctrl: SMHC_CTRL,
    pub smhc_clkdiv: SMHC_CLKDIV,
    pub smhc_tmout: SMHC_TMOUT,
    pub smhc_ctype: SMHC_CTYPE,
    pub smhc_blksiz: SMHC_BLKSIZ,
    pub smhc_bytcnt: SMHC_BYTCNT,
    pub smhc_cmd: SMHC_CMD,
    pub smhc_cmdarg: SMHC_CMDARG,
    pub smhc_resp0: SMHC_RESP0,
    pub smhc_resp1: SMHC_RESP1,
    pub smhc_resp2: SMHC_RESP2,
    pub smhc_resp3: SMHC_RESP3,
    pub smhc_intmask: SMHC_INTMASK,
    pub smhc_mintsts: SMHC_MINTSTS,
    pub smhc_rintsts: SMHC_RINTSTS,
    pub smhc_status: SMHC_STATUS,
    pub smhc_fifoth: SMHC_FIFOTH,
    pub smhc_funs: SMHC_FUNS,
    pub smhc_tbc0: SMHC_TBC0,
    pub smhc_tbc1: SMHC_TBC1,
    pub smhc_dbgc: SMHC_DBGC,
    pub smhc_csdc: SMHC_CSDC,
    pub smhc_a12a: SMHC_A12A,
    pub smhc_ntsr: SMHC_NTSR,
    pub smhc_hwrst: SMHC_HWRST,
    pub smhc_idmac: SMHC_IDMAC,
    pub smhc_dlba: SMHC_DLBA,
    pub smhc_idst: SMHC_IDST,
    pub smhc_idie: SMHC_IDIE,
    pub smhc_thld: SMHC_THLD,
    pub smhc_sfc: SMHC_SFC,
    pub smhc_a23a: SMHC_A23A,
    pub emmc_ddr_sbit_det: EMMC_DDR_SBIT_DET,
    pub smhc_ext_cmd: SMHC_EXT_CMD,
    pub smhc_ext_resp: SMHC_EXT_RESP,
    pub smhc_drv_dl: SMHC_DRV_DL,
    pub smhc_smap_dl: SMHC_SMAP_DL,
    pub smhc_ds_dl: SMHC_DS_DL,
    pub smhc_hs400_dl: SMHC_HS400_DL,
    pub smhc_fifo: SMHC_FIFO,
    /* private fields */

}
Expand description

Register block

Fields§

§smhc_ctrl: SMHC_CTRL

0x00 - Control Register

§smhc_clkdiv: SMHC_CLKDIV

0x04 - Clock Control Register

§smhc_tmout: SMHC_TMOUT

0x08 - Time Out Register

§smhc_ctype: SMHC_CTYPE

0x0c - Bus Width Register

§smhc_blksiz: SMHC_BLKSIZ

0x10 - Block Size Register

§smhc_bytcnt: SMHC_BYTCNT

0x14 - Byte Count Register

§smhc_cmd: SMHC_CMD

0x18 - Command Register

§smhc_cmdarg: SMHC_CMDARG

0x1c - Command Argument Register

§smhc_resp0: SMHC_RESP0

0x20 - Response 0 Register

§smhc_resp1: SMHC_RESP1

0x24 - Response 1 Register

§smhc_resp2: SMHC_RESP2

0x28 - Response 2 Register

§smhc_resp3: SMHC_RESP3

0x2c - Response 3 Register

§smhc_intmask: SMHC_INTMASK

0x30 - Interrupt Mask Register

§smhc_mintsts: SMHC_MINTSTS

0x34 - Masked Interrupt Status Register

§smhc_rintsts: SMHC_RINTSTS

0x38 - Raw Interrupt Status Register

§smhc_status: SMHC_STATUS

0x3c - Status Register

§smhc_fifoth: SMHC_FIFOTH

0x40 - FIFO Water Level Register

§smhc_funs: SMHC_FUNS

0x44 - FIFO Function Select Register

§smhc_tbc0: SMHC_TBC0

0x48 - Transferred Byte Count between Controller and Card

§smhc_tbc1: SMHC_TBC1

0x4c - Transferred Byte Count between Host Memory and Internal FIFO

§smhc_dbgc: SMHC_DBGC

0x50 - Current Debug Control Register

§smhc_csdc: SMHC_CSDC

0x54 - CRC Status Detect Control Registers

§smhc_a12a: SMHC_A12A

0x58 - Auto Command 12 Argument Register

§smhc_ntsr: SMHC_NTSR

0x5c - SD New Timing Set Register

§smhc_hwrst: SMHC_HWRST

0x78 - Hardware Reset Register

§smhc_idmac: SMHC_IDMAC

0x80 - IDMAC Control Register

§smhc_dlba: SMHC_DLBA

0x84 - Descriptor List Base Address Register

§smhc_idst: SMHC_IDST

0x88 - IDMAC Status Register

§smhc_idie: SMHC_IDIE

0x8c - IDMAC Interrupt Enable Register

§smhc_thld: SMHC_THLD

0x100 - Card Threshold Control Register

§smhc_sfc: SMHC_SFC

0x104 - Sample FIFO Control Register

§smhc_a23a: SMHC_A23A

0x108 - Auto Command 23 Argument Register

§emmc_ddr_sbit_det: EMMC_DDR_SBIT_DET

0x10c - eMMC4.5 DDR Start Bit Detection Control Register

§smhc_ext_cmd: SMHC_EXT_CMD

0x138 - Extended Command Register

§smhc_ext_resp: SMHC_EXT_RESP

0x13c - Extended Response Register

§smhc_drv_dl: SMHC_DRV_DL

0x140 - Drive Delay Control Register

§smhc_smap_dl: SMHC_SMAP_DL

0x144 - Sample Delay Control Register

§smhc_ds_dl: SMHC_DS_DL

0x148 - Data Strobe Delay Control Register

§smhc_hs400_dl: SMHC_HS400_DL

0x14c - HS400 Delay Control Register

§smhc_fifo: SMHC_FIFO

0x200 - Read/Write FIFO

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