Struct d1_pac::tcon_lcd0::fsync_gen_ctrl::R

pub struct R(/* private fields */);

Register fsync_gen_ctrl reader

Implementations

impl R

pub fn fsync_gen_en(&self) -> FSYNC_GEN_EN_R

Bit 0 - Fsync Generate Enable

pub fn sel_vsync_en(&self) -> SEL_VSYNC_EN_R

Bit 1 - Select Vsync Enable

pub fn hsync_pol_sel(&self) -> HSYNC_POL_SEL_R

Bit 2 - Hsync Polarity Select

pub fn sensor_dis_value(&self) -> SENSOR_DIS_VALUE_R

Bit 4 - Sensor Disable Value

pub fn sensor_act0_value(&self) -> SENSOR_ACT0_VALUE_R

Bit 5 - Sensor Active0 Value

pub fn sensor_act1_value(&self) -> SENSOR_ACT1_VALUE_R

Bit 6 - Sensor Active1 Value

pub fn sensor_dis_time(&self) -> SENSOR_DIS_TIME_R

Bits 8:18 - Delay 0-2047 Hsync Period

When hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.

When hsync_pol_sel is 1, the actual delay is sensor_dis_time.

Methods from Deref<Target = R<FSYNC_GEN_CTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<FSYNC_GEN_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<FSYNC_GEN_CTRL_SPEC>> for R

fn from(reader: R<FSYNC_GEN_CTRL_SPEC>) -> Self

Converts to this type from the input type.