Struct d1_pac::tcon_lcd0::fsync_gen_ctrl::W
source · pub struct W(/* private fields */);
Expand description
Register fsync_gen_ctrl
writer
Implementations§
source§impl W
impl W
sourcepub fn fsync_gen_en(&mut self) -> FSYNC_GEN_EN_W<'_, 0>
pub fn fsync_gen_en(&mut self) -> FSYNC_GEN_EN_W<'_, 0>
Bit 0 - Fsync Generate Enable
sourcepub fn sel_vsync_en(&mut self) -> SEL_VSYNC_EN_W<'_, 1>
pub fn sel_vsync_en(&mut self) -> SEL_VSYNC_EN_W<'_, 1>
Bit 1 - Select Vsync Enable
sourcepub fn hsync_pol_sel(&mut self) -> HSYNC_POL_SEL_W<'_, 2>
pub fn hsync_pol_sel(&mut self) -> HSYNC_POL_SEL_W<'_, 2>
Bit 2 - Hsync Polarity Select
sourcepub fn sensor_dis_value(&mut self) -> SENSOR_DIS_VALUE_W<'_, 4>
pub fn sensor_dis_value(&mut self) -> SENSOR_DIS_VALUE_W<'_, 4>
Bit 4 - Sensor Disable Value
sourcepub fn sensor_act0_value(&mut self) -> SENSOR_ACT0_VALUE_W<'_, 5>
pub fn sensor_act0_value(&mut self) -> SENSOR_ACT0_VALUE_W<'_, 5>
Bit 5 - Sensor Active0 Value
sourcepub fn sensor_act1_value(&mut self) -> SENSOR_ACT1_VALUE_W<'_, 6>
pub fn sensor_act1_value(&mut self) -> SENSOR_ACT1_VALUE_W<'_, 6>
Bit 6 - Sensor Active1 Value
sourcepub fn sensor_dis_time(&mut self) -> SENSOR_DIS_TIME_W<'_, 8>
pub fn sensor_dis_time(&mut self) -> SENSOR_DIS_TIME_W<'_, 8>
Bits 8:18 - Delay 0-2047 Hsync Period
When hsync_pol_sel is 0, the actual delay is sensor_dis_time-1.
When hsync_pol_sel is 1, the actual delay is sensor_dis_time.
Methods from Deref<Target = W<FSYNC_GEN_CTRL_SPEC>>§
Trait Implementations§
Auto Trait Implementations§
impl Freeze for W
impl RefUnwindSafe for W
impl Send for W
impl Sync for W
impl Unpin for W
impl UnwindSafe for W
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more