Struct d1_pac::tcon_lcd0::lcd_cpu_if::R

pub struct R(/* private fields */);

Register lcd_cpu_if reader

Implementations

impl R

pub fn tri_en(&self) -> TRI_EN_R

Bit 0 - Enable trigger mode

pub fn tri_start(&self) -> TRI_START_R

Bit 1 - Software must make sure that write ‘1’ only when this flag is ‘0’.

Writing ‘1’ starts a frame flush and writing ‘0’ has no effect.

This flag indicates the frame flush is running.

pub fn tri_fifo_en(&self) -> TRI_FIFO_EN_R

Bit 2 - Enable the trigger FIFO

pub fn tri_fifo_bist_en(&self) -> TRI_FIFO_BIST_EN_R

Bit 3 - Entry address is 0xFF8

pub fn flush(&self) -> FLUSH_R

Bit 16 - Direct transfer mode

If it is enabled, FIFO1 is regardless of the HV timing, the pixels data keep being transferred unless the input FIFO was empty.

Data output rate is controlled by DCLK.

pub fn auto(&self) -> AUTO_R

Bit 17 - Auto transfer mode

If it is 1, all the valid data during this frame are written to panel.

Note: This bit is sampled by Vsync.

pub fn rd_flag(&self) -> RD_FLAG_R

Bit 22 - The status of read operation.

pub fn wr_flag(&self) -> WR_FLAG_R

Bit 23 - The status of write operation.

pub fn ca(&self) -> CA_R

Bit 25 - Pin A1 value in 8080 mode WR/RD execute

pub fn da(&self) -> DA_R

Bit 26 - Pin A1 value in 8080 mode auto/flash states

pub fn cpu_mode(&self) -> CPU_MODE_R

Bits 28:31 - Set the cpu interface work mode

Methods from Deref<Target = R<LCD_CPU_IF_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<LCD_CPU_IF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<LCD_CPU_IF_SPEC>> for R

fn from(reader: R<LCD_CPU_IF_SPEC>) -> Self

Converts to this type from the input type.