Struct d1_pac::tcon_lcd0::lcd_cpu_if::W

pub struct W(/* private fields */);

Register lcd_cpu_if writer

Implementations

impl W

pub fn tri_en(&mut self) -> TRI_EN_W<'_, 0>

Bit 0 - Enable trigger mode

pub fn tri_start(&mut self) -> TRI_START_W<'_, 1>

Bit 1 - Software must make sure that write ‘1’ only when this flag is ‘0’.

Writing ‘1’ starts a frame flush and writing ‘0’ has no effect.

This flag indicates the frame flush is running.

pub fn tri_fifo_en(&mut self) -> TRI_FIFO_EN_W<'_, 2>

Bit 2 - Enable the trigger FIFO

pub fn tri_fifo_bist_en(&mut self) -> TRI_FIFO_BIST_EN_W<'_, 3>

Bit 3 - Entry address is 0xFF8

pub fn flush(&mut self) -> FLUSH_W<'_, 16>

Bit 16 - Direct transfer mode

If it is enabled, FIFO1 is regardless of the HV timing, the pixels data keep being transferred unless the input FIFO was empty.

Data output rate is controlled by DCLK.

pub fn auto(&mut self) -> AUTO_W<'_, 17>

Bit 17 - Auto transfer mode

If it is 1, all the valid data during this frame are written to panel.

Note: This bit is sampled by Vsync.

pub fn ca(&mut self) -> CA_W<'_, 25>

Bit 25 - Pin A1 value in 8080 mode WR/RD execute

pub fn da(&mut self) -> DA_W<'_, 26>

Bit 26 - Pin A1 value in 8080 mode auto/flash states

pub fn cpu_mode(&mut self) -> CPU_MODE_W<'_, 28>

Bits 28:31 - Set the cpu interface work mode

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<LCD_CPU_IF_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<LCD_CPU_IF_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<LCD_CPU_IF_SPEC>> for W

fn from(writer: W<LCD_CPU_IF_SPEC>) -> Self

Converts to this type from the input type.