Module d1_pac::tcon_lcd0::lcd_io_pol

LCD IO Polarity Register

Structs

• LCD_IO_POL_SPEC
  LCD IO Polarity Register
• R
  Register lcd_io_pol reader
• W
  Register lcd_io_pol writer

Enums

• DCLK_SEL_A
  Set the phase offset of clock and data in hv mode.
• IO_INV_A
  Enable invert function of IO[i]
• IO_OUTPUT_SEL_A
  When it is set as ‘1’, the d[23:0], io0, io1, io3 are sync to dclk.

Type Aliases

• DATA_INV_R
  Field data_inv reader - LCD output port D[23:0] polarity control, with independent bit control.
• DATA_INV_W
  Field data_inv writer - LCD output port D[23:0] polarity control, with independent bit control.
• DCLK_SEL_R
  Field dclk_sel reader - Set the phase offset of clock and data in hv mode.
• DCLK_SEL_W
  Field dclk_sel writer - Set the phase offset of clock and data in hv mode.
• IO_INV_R
  Field io_inv[0-3] reader - Enable invert function of IO[i]
• IO_INV_W
  Field io_inv[0-3] writer - Enable invert function of IO[i]
• IO_OUTPUT_SEL_R
  Field io_output_sel reader - When it is set as ‘1’, the d[23:0], io0, io1, io3 are sync to dclk.
• IO_OUTPUT_SEL_W
  Field io_output_sel writer - When it is set as ‘1’, the d[23:0], io0, io1, io3 are sync to dclk.