Type Alias d1_pac::tcon_lcd0::lcd_io_pol::DCLK_SEL_W

pub type DCLK_SEL_W<'a, const O: u8> = FieldWriter<'a, u32, LCD_IO_POL_SPEC, u8, DCLK_SEL_A, 3, O>;

Field dclk_sel writer - Set the phase offset of clock and data in hv mode.

Aliased Type

struct DCLK_SEL_W<'a, const O: u8> { /* private fields */ }

Implementations

impl<'a, const O: u8> DCLK_SEL_W<'a, O>

pub fn dclk0(self) -> &'a mut W

Used DCLK0 (normal phase offset)

pub fn dclk1(self) -> &'a mut W

Used DCLK1 (1/3 phase offset)

pub fn dclk2(self) -> &'a mut W

Used DCLK2 (2/3 phase offset)

pub fn dclk02_0(self) -> &'a mut W

DCLK0/2 phase 0

pub fn dclk02_90(self) -> &'a mut W

DCLK0/2 phase 90