Struct d1_pac::tcon_lcd0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 44 fields
    pub lcd_gctl: LCD_GCTL,
    pub lcd_gint0: LCD_GINT0,
    pub lcd_gint1: LCD_GINT1,
    pub lcd_frm_ctl: LCD_FRM_CTL,
    pub lcd_frm_seed: [LCD_FRM_SEED; 6],
    pub lcd_frm_tab: [LCD_FRM_TAB; 4],
    pub lcd_3d_fifo: LCD_3D_FIFO,
    pub lcd_ctl: LCD_CTL,
    pub lcd_dclk: LCD_DCLK,
    pub lcd_basic0: LCD_BASIC0,
    pub lcd_basic1: LCD_BASIC1,
    pub lcd_basic2: LCD_BASIC2,
    pub lcd_basic3: LCD_BASIC3,
    pub lcd_hv_if: LCD_HV_IF,
    pub lcd_cpu_if: LCD_CPU_IF,
    pub lcd_cpu_wr: LCD_CPU_WR,
    pub lcd_cpu_rd: [LCD_CPU_RD; 2],
    pub lcd_lvds_if: LCD_LVDS_IF,
    pub lcd_io_pol: LCD_IO_POL,
    pub lcd_io_tri: LCD_IO_TRI,
    pub lcd_debug: LCD_DEBUG,
    pub lcd_ceu_ctl: LCD_CEU_CTL,
    pub lcd_ceu_coef_mul: [LCD_CEU_COEF_MUL; 3],
    pub lcd_ceu_coef_add0: LCD_CEU_COEF_ADD,
    pub lcd_ceu_coef_add1: LCD_CEU_COEF_ADD,
    pub lcd_ceu_coef_add2: LCD_CEU_COEF_ADD,
    pub lcd_ceu_coef_rang: [LCD_CEU_COEF_RANG; 3],
    pub lcd_cpu_tri0: LCD_CPU_TRI0,
    pub lcd_cpu_tri1: LCD_CPU_TRI1,
    pub lcd_cpu_tri2: LCD_CPU_TRI2,
    pub lcd_cpu_tri3: LCD_CPU_TRI3,
    pub lcd_cpu_tri4: LCD_CPU_TRI4,
    pub lcd_cpu_tri5: LCD_CPU_TRI5,
    pub lcd_cmap_ctl: LCD_CMAP_CTL,
    pub lcd_cmap_odd: [LCD_CMAP_ODD; 2],
    pub lcd_cmap_even: [LCD_CMAP_EVEN; 2],
    pub lcd_safe_period: LCD_SAFE_PERIOD,
    pub lcd_lvds_ana: [LCD_LVDS_ANA; 2],
    pub fsync_gen_ctrl: FSYNC_GEN_CTRL,
    pub fsync_gen_dly: FSYNC_GEN_DLY,
    pub lcd_sync_ctl: LCD_SYNC_CTL,
    pub lcd_sync_pos: LCD_SYNC_POS,
    pub lcd_slave_stop_pos: LCD_SLAVE_STOP_POS,
    pub lcd_gamma_table: [LCD_GAMMA_TABLE; 256],
    /* private fields */

}
Expand description

Register block

Fields§

§lcd_gctl: LCD_GCTL

0x00 - LCD Global Control Register

§lcd_gint0: LCD_GINT0

0x04 - LCD Global Interrupt Register0

§lcd_gint1: LCD_GINT1

0x08 - LCD Global Interrupt Register1

§lcd_frm_ctl: LCD_FRM_CTL

0x10 - LCD FRM Control Register

§lcd_frm_seed: [LCD_FRM_SEED; 6]

0x14..0x2c - LCD FRM Seed Register

§lcd_frm_tab: [LCD_FRM_TAB; 4]

0x2c..0x3c - LCD FRM Table Register

§lcd_3d_fifo: LCD_3D_FIFO

0x3c - LCD 3D FIFO Register

§lcd_ctl: LCD_CTL

0x40 - LCD Control Register

§lcd_dclk: LCD_DCLK

0x44 - LCD Data Clock Register

§lcd_basic0: LCD_BASIC0

0x48 - LCD Basic Timing Register0

§lcd_basic1: LCD_BASIC1

0x4c - LCD Basic Timing Register1

§lcd_basic2: LCD_BASIC2

0x50 - LCD Basic Timing Register2

§lcd_basic3: LCD_BASIC3

0x54 - LCD Basic Timing Register3

§lcd_hv_if: LCD_HV_IF

0x58 - LCD HV Panel Interface Register

§lcd_cpu_if: LCD_CPU_IF

0x60 - LCD CPU Panel Interface Register

§lcd_cpu_wr: LCD_CPU_WR

0x64 - LCD CPU Panel Write Data Register

§lcd_cpu_rd: [LCD_CPU_RD; 2]

0x68..0x70 - LCD CPU Panel Read Data Register[i]

§lcd_lvds_if: LCD_LVDS_IF

0x84 - LCD LVDS Configure Register

§lcd_io_pol: LCD_IO_POL

0x88 - LCD IO Polarity Register

§lcd_io_tri: LCD_IO_TRI

0x8c - LCD IO Control Register

§lcd_debug: LCD_DEBUG

0xfc - LCD Debug Register

§lcd_ceu_ctl: LCD_CEU_CTL

0x100 - LCD CEU Control Register

§lcd_ceu_coef_mul: [LCD_CEU_COEF_MUL; 3]

0x110..0x11c - LCD CEU Coefficient Register0

§lcd_ceu_coef_add0: LCD_CEU_COEF_ADD

0x11c - LCD CEU Coefficient Register1

§lcd_ceu_coef_add1: LCD_CEU_COEF_ADD

0x12c - LCD CEU Coefficient Register1

§lcd_ceu_coef_add2: LCD_CEU_COEF_ADD

0x13c - LCD CEU Coefficient Register1

§lcd_ceu_coef_rang: [LCD_CEU_COEF_RANG; 3]

0x140..0x14c - LCD CEU Coefficient Register2

§lcd_cpu_tri0: LCD_CPU_TRI0

0x160 - LCD CPU Panel Trigger Register0

§lcd_cpu_tri1: LCD_CPU_TRI1

0x164 - LCD CPU Panel Trigger Register1

§lcd_cpu_tri2: LCD_CPU_TRI2

0x168 - LCD CPU Panel Trigger Register2

§lcd_cpu_tri3: LCD_CPU_TRI3

0x16c - LCD CPU Panel Trigger Register3

§lcd_cpu_tri4: LCD_CPU_TRI4

0x170 - LCD CPU Panel Trigger Register4

§lcd_cpu_tri5: LCD_CPU_TRI5

0x174 - LCD CPU Panel Trigger Register5

§lcd_cmap_ctl: LCD_CMAP_CTL

0x180 - LCD Color Map Control Register

§lcd_cmap_odd: [LCD_CMAP_ODD; 2]

0x190..0x198 - LCD Color Map Odd Line Register[i]

§lcd_cmap_even: [LCD_CMAP_EVEN; 2]

0x198..0x1a0 - LCD Color Map Even Line Register[i]

§lcd_safe_period: LCD_SAFE_PERIOD

0x1f0 - LCD Safe Period Register

§lcd_lvds_ana: [LCD_LVDS_ANA; 2]

0x220..0x228 - LCD LVDS Analog Register [i]

§fsync_gen_ctrl: FSYNC_GEN_CTRL

0x228 - FSYNC_GEN_CTRL

§fsync_gen_dly: FSYNC_GEN_DLY

0x22c - FSYNC_GEN_DLY

§lcd_sync_ctl: LCD_SYNC_CTL

0x230 - LCD Sync Control Register

§lcd_sync_pos: LCD_SYNC_POS

0x234 - LCD Sync Position Register

§lcd_slave_stop_pos: LCD_SLAVE_STOP_POS

0x238 - LCD Slave Stop Position Register

§lcd_gamma_table: [LCD_GAMMA_TABLE; 256]

0x400..0x800 - LCD Gamma Table Register

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