Struct d1_pac::timer::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 19 fields
    pub tmr_irq_en: TMR_IRQ_EN,
    pub tmr_irq_sta: TMR_IRQ_STA,
    pub tmr0_ctrl: TMR_CTRL,
    pub tmr0_intv_value: TMR_INTV_VALUE,
    pub tmr0_cur_value: TMR_CUR_VALUE,
    pub tmr1_ctrl: TMR_CTRL,
    pub tmr1_intv_value: TMR_INTV_VALUE,
    pub tmr1_cur_value: TMR_CUR_VALUE,
    pub wdog_irq_en: WDOG_IRQ_EN,
    pub wdog_irq_sta: WDOG_IRQ_STA,
    pub wdog_soft_rst: WDOG_SOFT_RST,
    pub wdog_ctrl: WDOG_CTRL,
    pub wdog_cfg: WDOG_CFG,
    pub wdog_mode: WDOG_MODE,
    pub wdog_output_cfg: WDOG_OUTPUT_CFG,
    pub avs_cnt_ctl: AVS_CNT_CTL,
    pub avs_cnt0: AVS_CNT0,
    pub avs_cnt1: AVS_CNT1,
    pub avs_cnt_div: AVS_CNT_DIV,
    /* private fields */

}
Expand description

Register block

Fields§

§tmr_irq_en: TMR_IRQ_EN

0x00 - Timer IRQ Enable Register

§tmr_irq_sta: TMR_IRQ_STA

0x04 - Timer Status Register

§tmr0_ctrl: TMR_CTRL

0x10 - Timer IRQ Enable Register

§tmr0_intv_value: TMR_INTV_VALUE

0x14 - Timer Interval Value Register

§tmr0_cur_value: TMR_CUR_VALUE

0x18 - Timer Current Value Register

§tmr1_ctrl: TMR_CTRL

0x20 - Timer IRQ Enable Register

§tmr1_intv_value: TMR_INTV_VALUE

0x24 - Timer Interval Value Register

§tmr1_cur_value: TMR_CUR_VALUE

0x28 - Timer Current Value Register

§wdog_irq_en: WDOG_IRQ_EN

0xa0 - Watchdog IRQ Enable Register

§wdog_irq_sta: WDOG_IRQ_STA

0xa4 - Watchdog Status Register

§wdog_soft_rst: WDOG_SOFT_RST

0xa8 - Watchdog Software Reset Register

§wdog_ctrl: WDOG_CTRL

0xb0 - Watchdog Control Register

§wdog_cfg: WDOG_CFG

0xb4 - Watchdog Configuration Register

§wdog_mode: WDOG_MODE

0xb8 - Watchdog Mode Register

§wdog_output_cfg: WDOG_OUTPUT_CFG

0xbc - Watchdog Output Configuration Register

§avs_cnt_ctl: AVS_CNT_CTL

0xc0 - AVS Counter Control Register

§avs_cnt0: AVS_CNT0

0xc4 - AVS Counter 0 Register

§avs_cnt1: AVS_CNT1

0xc8 - AVS Counter 1 Register

§avs_cnt_div: AVS_CNT_DIV

0xcc - AVS Counter Divisor Register

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