Struct d1_pac::twi::RegisterBlock

source ·
#[repr(C)]
pub struct RegisterBlock {
Show 19 fields pub twi_addr: TWI_ADDR, pub twi_xaddr: TWI_XADDR, pub twi_data: TWI_DATA, pub twi_cntr: TWI_CNTR, pub twi_stat: TWI_STAT, pub twi_ccr: TWI_CCR, pub twi_srst: TWI_SRST, pub twi_efr: TWI_EFR, pub twi_lcr: TWI_LCR, pub twi_drv_ctrl: TWI_DRV_CTRL, pub twi_drv_cfg: TWI_DRV_CFG, pub twi_drv_slv: TWI_DRV_SLV, pub twi_drv_fmt: TWI_DRV_FMT, pub twi_drv_bus_ctrl: TWI_DRV_BUS_CTRL, pub twi_drv_int_ctrl: TWI_DRV_INT_CTRL, pub twi_drv_dma_cfg: TWI_DRV_DMA_CFG, pub twi_drv_fifo_con: TWI_DRV_FIFO_CON, pub twi_drv_send_fifo_acc: TWI_DRV_SEND_FIFO_ACC, pub twi_drv_recv_fifo_acc: TWI_DRV_RECV_FIFO_ACC, /* private fields */
}
Expand description

Register block

Fields§

§twi_addr: TWI_ADDR

0x00 - TWI Slave Address Register

§twi_xaddr: TWI_XADDR

0x04 - TWI Extended Slave Address Register

§twi_data: TWI_DATA

0x08 - TWI Data Byte Register

§twi_cntr: TWI_CNTR

0x0c - TWI Control Register

§twi_stat: TWI_STAT

0x10 - TWI Status Register

§twi_ccr: TWI_CCR

0x14 - TWI Clock Control Register

§twi_srst: TWI_SRST

0x18 - TWI Software Reset Register

§twi_efr: TWI_EFR

0x1c - TWI Enhance Feature Register

§twi_lcr: TWI_LCR

0x20 - TWI Line Control Register

§twi_drv_ctrl: TWI_DRV_CTRL

0x200 - TWI_DRV Control Register

§twi_drv_cfg: TWI_DRV_CFG

0x204 - TWI_DRV Transmission Configuration Register

§twi_drv_slv: TWI_DRV_SLV

0x208 - TWI_DRV Slave ID Register

§twi_drv_fmt: TWI_DRV_FMT

0x20c - TWI_DRV Packet Format Register

§twi_drv_bus_ctrl: TWI_DRV_BUS_CTRL

0x210 - TWI_DRV Bus Control Register

§twi_drv_int_ctrl: TWI_DRV_INT_CTRL

0x214 - TWI_DRV Interrupt Control Register

§twi_drv_dma_cfg: TWI_DRV_DMA_CFG

0x218 - TWI_DRV DMA Configure Register

§twi_drv_fifo_con: TWI_DRV_FIFO_CON

0x21c - TWI_DRV FIFO Content Register

§twi_drv_send_fifo_acc: TWI_DRV_SEND_FIFO_ACC

0x300 - TWI_DRV Send Data FIFO Access Register

§twi_drv_recv_fifo_acc: TWI_DRV_RECV_FIFO_ACC

0x304 - TWI_DRV Receive Data FIFO Access Register

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