Struct d1_pac::uart::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 28 fields
    pub lcr: LCR,
    pub mcr: MCR,
    pub lsr: LSR,
    pub msr: MSR,
    pub sch: SCH,
    pub usr: USR,
    pub tfl: TFL,
    pub rfl: RFL,
    pub hsk: HSK,
    pub dma_req_en: DMA_REQ_EN,
    pub halt: HALT,
    pub dbg_dll: DBG_DLL,
    pub dbg_dlh: DBG_DLH,
    pub fcc: FCC,
    pub rxdma_ctrl: RXDMA_CTRL,
    pub rxdma_str: RXDMA_STR,
    pub rxdma_sta: RXDMA_STA,
    pub rxdma_lmt: RXDMA_LMT,
    pub rxdma_saddrl: RXDMA_SADDRL,
    pub rxdma_saddrh: RXDMA_SADDRH,
    pub rxdma_bl: RXDMA_BL,
    pub rxdma_ie: RXDMA_IE,
    pub rxdma_is: RXDMA_IS,
    pub rxdma_waddrl: RXDMA_WADDRL,
    pub rxdma_waddrh: RXDMA_WADDRH,
    pub rxdma_raddrl: RXDMA_RADDRL,
    pub rxdma_raddrh: RXDMA_RADDRH,
    pub rxdma_dcnt: RXDMA_DCNT,
    /* private fields */

}
Expand description

Register block

Fields§

§lcr: LCR

0x0c - UART Line Control Register

§mcr: MCR

0x10 - UART Modem Control Register

§lsr: LSR

0x14 - UART Line Status Register

§msr: MSR

0x18 - UART Modem Status Register

§sch: SCH

0x1c - UART Scratch Register

§usr: USR

0x7c - UART Status Register

§tfl: TFL

0x80 - UART Transmit FIFO Level Register

§rfl: RFL

0x84 - UART Receive FIFO Level Register

§hsk: HSK

0x88 - UART DMA Handshake Configuration Register

§dma_req_en: DMA_REQ_EN

0x8c - UART DMA Request Enable Register

§halt: HALT

0xa4 - UART Halt TX Register

§dbg_dll: DBG_DLL

0xb0 - UART Debug DLL Register

§dbg_dlh: DBG_DLH

0xb4 - UART Debug DLH Register

§fcc: FCC

0xf0 - UART FIFO Clock Control Register

§rxdma_ctrl: RXDMA_CTRL

0x100 - UART RXDMA Control Register

§rxdma_str: RXDMA_STR

0x104 - UART RXDMA Start Register

§rxdma_sta: RXDMA_STA

0x108 - UART RXDMA Status Register

§rxdma_lmt: RXDMA_LMT

0x10c - UART RXDMA Limit Register

§rxdma_saddrl: RXDMA_SADDRL

0x110 - UART RXDMA Buffer Start Address Low Register

§rxdma_saddrh: RXDMA_SADDRH

0x114 - UART RXDMA Buffer Start Address High Register

§rxdma_bl: RXDMA_BL

0x118 - UART RXDMA Buffer Length Register

§rxdma_ie: RXDMA_IE

0x120 - UART RXDMA Interrupt Enable Register

§rxdma_is: RXDMA_IS

0x124 - UART RXDMA Interrupt Status Register

§rxdma_waddrl: RXDMA_WADDRL

0x128 - UART RXDMA Write Address Low Register

§rxdma_waddrh: RXDMA_WADDRH

0x12c - UART RXDMA Write Address High Register

§rxdma_raddrl: RXDMA_RADDRL

0x130 - UART RXDMA Read Address Low Register

§rxdma_raddrh: RXDMA_RADDRH

0x134 - UART RXDMA Read Address High Register

§rxdma_dcnt: RXDMA_DCNT

0x138 - UART RXDMA Data Count Register

Implementations§

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impl RegisterBlock

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pub const fn dll(&self) -> &DLL

0x00 - UART Divisor Latch Low Register

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pub const fn thr(&self) -> &THR

0x00 - UART Transmit Holding Register

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pub const fn rbr(&self) -> &RBR

0x00 - UART Receive Buffer Register

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pub const fn ier(&self) -> &IER

0x04 - UART Interrupt Enable Register

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pub const fn dlh(&self) -> &DLH

0x04 - UART Divisor Latch High Register

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pub const fn fcr(&self) -> &FCR

0x08 - UART FIFO Control Register

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pub const fn iir(&self) -> &IIR

0x08 - UART Interrupt Identity Register

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