Struct d1_pac::usb1::ehci_operational::portsc::R

pub struct R(/* private fields */);

Register portsc reader

Implementations

impl R

pub fn current_connect_status(&self) -> CURRENT_CONNECT_STATUS_R

Bit 0 - Current Connect Status

Device is present on port when the value of this field is a one, and no device is present on port when the value of this field is a zero. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change(Bit 1) to be set.

This field is zero if Port Power zero.

pub fn connect_status_change(&self) -> CONNECT_STATUS_CHANGE_R

Bit 1 - Connect Status Change

1=Change in Current Connect Status

0=No change

Indicates a change has occurred in the current connect status of the port. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be ‘setting’ an already-set bit. Software sets this bit to 0 by writing a 1 to it.

This field is zero if Port Power is zero.

pub fn port_enabled_disabled(&self) -> PORT_ENABLED_DISABLED_R

Bit 2 - Port Enabled/Disabled

1=Enable

0=Disable

Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. The host controller will only set this bit to a one when the reset sequence determines that the attached device is a high- speed device.

Ports can be disabled by either a fault condition(disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.

When the port is disabled, downstream propagation of data is blocked on this port except for reset.

The default value of this field is ‘0’.

This field is zero if Port Power is zero.

pub fn port_enable_disable_change(&self) -> PORT_ENABLE_DISABLE_CHANGE_R

Bit 3 - Port Enable/Disable Change

1 = Port enabled/disabled status has changed

0 = No change

For the root hub, this bit gets set to a one only when a port is disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it.

This field is zero if Port Power is zero.

pub fn over_current_active(&self) -> OVER_CURRENT_ACTIVE_R

Bit 4 - Over-current Active

0 = This port does not have an over-current condition

1 = This port currently has an over-current condition

This bit will automatically transition from a one to a zero when the over current condition is removed.

The default value of this bit is ‘0’.

pub fn over_current_change(&self) -> OVER_CURRENT_CHANGE_R

Bit 5 - Over-current Change

This bit gets set to a one when there is a change to Over-current Active. Software clears this bit by writing a one to this bit position.

pub fn force_port_resume(&self) -> FORCE_PORT_RESUME_R

Bit 6 - Force Port Resume

1 = Resume detected/driven on port. 0 = No resume (K-state) detected/driven on port. Default value = 0.

This functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspend and software transitions this bit to a one, then the effects on the bus are undefined.

Software sets this bit to 1 to drive resume signaling. The Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host controller must not set the Port Change Detect bit.

Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed ‘K’) is driven on the port as long as this remains a one. Software must appropriately time the Resume and set this bit to a zero when the appropriate amount of time has elapsed. Writing a zero (from one) causes the port to return high-speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a one until the port has switched to high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to a zero.

This field is zero if Port Power is zero.

pub fn suspend(&self) -> SUSPEND_R

Bit 7 - Suspend

Port Enabled Bit and Suspend bit of this register define the port states

When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Not that the bit status does not change until the port is suspend and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB.

A write of zero to this bit is ignored by the host controller. The host controller will unconditionally set this bit to a zero when:

1. Software sets the Force Port Resume bit to a zero(from a one).
2. Software sets the Port Reset bit to a one(from a zero).

If host software sets this bit to a one when the port is not enabled(i.e. Port enabled bit is a zero), the results are undefined.

This field is zero if Port Power is zero.

The default value in this field is ‘0’.

pub fn port_reset(&self) -> PORT_RESET_R

Bit 8 - Port Reset

1=Port is in Reset. 0=Port is not in Reset. Default value = 0.

When software writes a one to this bit (from a zero), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate the bus reset sequence. Software must keep this bit at a one long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes.

Note: When software writes this bit to a one, it must also write a zero to the Port Enable bit.

Note that when software writes a zero to this bit there may be a delay before the bit status changes to a zero. The bit status will not read as a zero until after the reset has completed. If the port is in high-speed mode after reset is complete, the host controller will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from a one to a zero. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state with 2ms of software writing this bit to a zero. The HC Halted bit in the USBSTS register should be a zero before software attempts to use this bit. The host controller may hold Port Reset asserted to a one when the HC Halted bit is a one. This field is zero if Port Power is zero.

pub fn line_status(&self) -> LINE_STATUS_R

Bits 10:11 - Line Status

These bits relect the current logical levels of the D+ (bit11) and D- (bit10) signal lines. These bits are used for detection of low-speed USB devices prior to port reset and enable sequence. This read only field is valid only when the port enable bit is zero and the current connect status bit is set to a one.

pub fn port_owner(&self) -> PORT_OWNER_R

Bit 13 - Port Owner

This bit unconditionally goes to a 0b when the Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally goes to 1b whenever the Configured bit is zero. System software uses this field to release ownership of the port to selected host controller (in the event that the attached device is not a high-speed device).Software writes a one to this bit when the attached device is not a high-speed device. A one in this bit means that a companion host controller owns and controls the port. Default Value = 1b.

pub fn port_test_control(&self) -> PORT_TEST_CONTROL_R

Bits 16:19 - Port Test Control

The value in this field specifies the test mode of the port.

pub fn wkcnnt_e(&self) -> WKCNNT_E_R

Bit 20 - Wake on Connect Enable (WKCNNT_E)

Writing this bit to a one enable the port to be sensitive to device connects as wake-up events.

This field is zero if Port Power is zero.

The default value in this field is ‘0’.

pub fn wkdscnnt_e(&self) -> WKDSCNNT_E_R

Bit 21 - Wake on Disconnect Enable (WKDSCNNT_E)

Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.

This field is zero if Port Power is zero.

The default value in this field is ‘0’.

Methods from Deref<Target = R<PORTSC_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<PORTSC_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<PORTSC_SPEC>> for R

fn from(reader: R<PORTSC_SPEC>) -> Self

Converts to this type from the input type.