Struct d1_pac::usb1::ehci_operational::usbcmd::R

pub struct R(/* private fields */);

Register usbcmd reader

Implementations

impl R

pub fn run_stop(&self) -> RUN_STOP_R

Bit 0 - Run/Stop

When set to a 1, the Host Controller proceeds with execution of the schedule. When set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 micro-frames after software clears this bit. The HC Halted bit indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state.

Software must not write a one to this field unless the Host Controller is in the Halt State. The default value is 0x0.

pub fn host_controller_reset(&self) -> HOST_CONTROLLER_RESET_R

Bit 1 - Host Controller Reset

This control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset.

When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports.

All operational registers, including port registers and port state machines are set to their initial values. Port ownership reverts to the companion host controller(s). Software must reinitialize the host controller as described in Section 4.1 of the CHEI Specification in order to return the host controller to an operational state. This bit is set to zero by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register.

Software should not set this bit to a one when the HC Halted bit in the USBSTS register is a zero. Attempting to reset an actively running host controller will result in undefined behavior.

pub fn frame_list_size(&self) -> FRAME_LIST_SIZE_R

Bits 2:3 - This field is R/W only if Programmable Frame List Flag in the HCCPARAMS register is set to one. This field specifies the size of the Frame list.

pub fn periodic_schedule_enable(&self) -> PERIODIC_SCHEDULE_ENABLE_R

Bit 4 - Periodic Schedule Enable

This bit controls whether the host controller skips processing the Periodic Schedule.

pub fn asynchronous_schedule_enable(&self) -> ASYNCHRONOUS_SCHEDULE_ENABLE_R

Bit 5 - Asynchronous Schedule Enable

This bit controls whether the host controller skips processing the Asynchronous Schedule.

pub fn interrupt_on_async_advance_doorbell( &self, ) -> INTERRUPT_ON_ASYNC_ADVANCE_DOORBELL_R

Bit 6 - Interrupt on Async Advance Doorbell

This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the USBSTS. if the Interrupt on Async Advance Enable bit in the USBINTR register is a one then the host controller will assert an interrupt at the next interrupt threshold.

The host controller sets this bit to a zero after it has set the Interrupt on Async Advance status bit in the USBSTS register to a one.

Software should not write a one to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results.

pub fn light_host_controller_reset(&self) -> LIGHT_HOST_CONTROLLER_RESET_R

Bit 7 - Light Host Controller Reset (OPTIONAL)

This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or relationship to the companion host controllers. For example, the PORSTC registers should not be reset to their default values and the CF bit setting should not go to zero (retaining port ownership relationships). A host software read of this bit as zero indicates the Light Host Controller Reset has completed and it si safe for software to re- initialize the host controller. A host software read of this bit as a one indicates the Light Host

pub fn asynchronous_schedule_park_mode_count( &self, ) -> ASYNCHRONOUS_SCHEDULE_PARK_MODE_COUNT_R

Bits 8:9 - Asynchronous Schedule Park Mode Count (OPTIONAL)

Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this field defaults to 0x3 and is W/R. Otherwise it defaults to zero and is R. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid value are 0x1 to 0x3.Software must not write a zero to this bit when Park Mode Enable is a one as it will result in undefined behavior.

pub fn asynchronous_schedule_park_mode_enable( &self, ) -> ASYNCHRONOUS_SCHEDULE_PARK_MODE_ENABLE_R

Bit 11 - Asynchronous Schedule Park Mode Enable (OPTIONAL)

If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this bit defaults to a 1 and is R/W. Otherwise the bit must be a zero and is Read Only. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is zero, Park mode is disabled.

pub fn interrupt_threshold_control(&self) -> INTERRUPT_THRESHOLD_CONTROL_R

Bits 16:23 - Interrupt Threshold Control

The value in this field is used by system software to select the maximum rate at which the host controller will issue interrupts.

Methods from Deref<Target = R<USBCMD_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<USBCMD_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<USBCMD_SPEC>> for R

fn from(reader: R<USBCMD_SPEC>) -> Self

Converts to this type from the input type.