Struct d1_pac::usb1::ehci_operational::usbintr::W

pub struct W(/* private fields */);

Register usbintr writer

Implementations

impl W

pub fn usb_interrupt_enable(&mut self) -> USB_INTERRUPT_ENABLE_W<'_, 0>

Bit 0 - USB Interrupt Enable

When this bit is 1, and the USBINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.

The interrupt is acknowledged by software clearing the USBINT bit

pub fn usb_error_interrupt_enable( &mut self, ) -> USB_ERROR_INTERRUPT_ENABLE_W<'_, 1>

Bit 1 - USB Error Interrupt Enable

When this bit is 1, and the USBERRINT bit in the USBSTS register is 1,the host controller will issue an interrupt at the next interrupt threshold.

The interrupt is acknowledged by software clearing the USBERRINT bit.

pub fn port_change_interrupt_enable( &mut self, ) -> PORT_CHANGE_INTERRUPT_ENABLE_W<'_, 2>

Bit 2 - Port Change Interrupt Enable

When this bit is 1, and the Port Chang Detect bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Chang Detect bit.

pub fn frame_list_rollover_enable( &mut self, ) -> FRAME_LIST_ROLLOVER_ENABLE_W<'_, 3>

Bit 3 - Frame List Rollover Enable

When this bit is 1, and the Frame List Rollover bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit.

pub fn host_system_error_enable(&mut self) -> HOST_SYSTEM_ERROR_ENABLE_W<'_, 4>

Bit 4 - Host System Error Enable

When this bit is 1, and the Host System Error Status bit in the USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit.

pub fn interrupt_on_async_advance_enable( &mut self, ) -> INTERRUPT_ON_ASYNC_ADVANCE_ENABLE_W<'_, 5>

Bit 5 - Interrupt on Async Advance Enable

When this bit is 1, and the Interrupt on Async Advance bit in the USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<USBINTR_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<USBINTR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<USBINTR_SPEC>> for W

fn from(writer: W<USBINTR_SPEC>) -> Self

Converts to this type from the input type.