Struct d1_pac::usb1::ehci_operational::usbsts::R

pub struct R(/* private fields */);

Register usbsts reader

Implementations

impl R

pub fn usbint(&self) -> USBINT_R

Bit 0 - USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes)

pub fn usberrint(&self) -> USBERRINT_R

Bit 1 - USB Error Interrupt(USBERRINT)

The Host Controller sets this bit to 1 when completion of USB transaction results in an error condition(e.g. error counter underflow).If the TD on which the error interrupt occurred also had its IOC bit set, both. This bit and USBINT bit are set.

pub fn port_change_detect(&self) -> PORT_CHANGE_DETECT_R

Bit 2 - Port Change Detect

The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port’s Port Owner bit.

pub fn frame_list_rollover(&self) -> FRAME_LIST_ROLLOVER_R

Bit 3 - Frame List Rollover

The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX [12] toggles.

pub fn host_system_error(&self) -> HOST_SYSTEM_ERROR_R

Bit 4 - Host System Error

The Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs.

pub fn interrupt_on_async_advance(&self) -> INTERRUPT_ON_ASYNC_ADVANCE_R

Bit 5 - Interrupt on Async Advance

System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.

pub fn hc_halted(&self) -> HC_HALTED_R

Bit 12 - HC Halted

This bit is a zero whenever the Run/Stop bit is a one. The Host Controller Sets this bit to one after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller Hardware (e.g. internal error).

The default value is ‘1’

pub fn reclamation(&self) -> RECLAMATION_R

Bit 13 - Reclamation

This is a read-only status bit, which is used to detect an empty asynchronous schedule.

pub fn periodic_schedule_status(&self) -> PERIODIC_SCHEDULE_STATUS_R

Bit 14 - Periodic Schedule Status

The bit reports the current real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is enabled. The Host Controller is not required to disable or enable the Periodic Schedule when software transitions the bit in the USBCMD register. When this bit and the bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0).

pub fn asynchronous_schedule_status(&self) -> ASYNCHRONOUS_SCHEDULE_STATUS_R

Bit 15 - Asynchronous Schedule Status

The bit reports the current real status of Asynchronous Schedule. If this bit is a zero then the status of the Asynchronous Schedule is disabled. If this bit is a one then the status of the Asynchronous Schedule is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0).

Methods from Deref<Target = R<USBSTS_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<USBSTS_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<USBSTS_SPEC>> for R

fn from(reader: R<USBSTS_SPEC>) -> Self

Converts to this type from the input type.