Struct d1_pac::usb1::ehci_operational::usbsts::W

source ·

pub struct W(/* private fields */);

Expand description

Register usbsts writer

Implementations§

source §

impl W

source

pub fn usbint(&mut self) -> USBINT_W<'_, 0>

Bit 0 - USB Interrupt(USBINT) The Host Controller sets this bit to a one on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual number of bytes received was less than the expected number of bytes)

source

pub fn usberrint(&mut self) -> USBERRINT_W<'_, 1>

Bit 1 - USB Error Interrupt(USBERRINT)

The Host Controller sets this bit to 1 when completion of USB transaction results in an error condition(e.g. error counter underflow).If the TD on which the error interrupt occurred also had its IOC bit set, both. This bit and USBINT bit are set.

source

pub fn port_change_detect(&mut self) -> PORT_CHANGE_DETECT_W<'_, 2>

Bit 2 - Port Change Detect

The Host Controller sets this bit to a one when any port for which the Port Owner bit is set to zero has a change bit transition from a zero to a one or a Force Port Resume bit transition from a zero to a one as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Chang being set to a one after system software has relinquished ownership of a connected port by writing a one to a port’s Port Owner bit.

source

pub fn frame_list_rollover(&mut self) -> FRAME_LIST_ROLLOVER_W<'_, 3>

Bit 3 - Frame List Rollover

The Host Controller sets this bit to a one when the Frame List Index rolls over from its maximum value to zero. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size is 1024, the Frame Index Register rolls over every time FRINDEX [13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one every time FRINDEX [12] toggles.

source

pub fn host_system_error(&mut self) -> HOST_SYSTEM_ERROR_W<'_, 4>

Bit 4 - Host System Error

The Host Controller set this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs.

source

pub fn interrupt_on_async_advance( &mut self, ) -> INTERRUPT_ON_ASYNC_ADVANCE_W<'_, 5>

Bit 5 - Interrupt on Async Advance

System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD register. This status bit indicates the assertion of that interrupt source.

source