Struct d1_pac::usb1::ohci_control_status_partition::hc_interrupt_enable::W

pub struct W(/* private fields */);

Register hc_interrupt_enable writer

Implementations

impl W

pub fn scheduling_overrun(&mut self) -> SCHEDULING_OVERRUN_W<'_, 0>

Bit 0 - SchedulingOverrun Interrupt Enable

pub fn writeback_done_head(&mut self) -> WRITEBACK_DONE_HEAD_W<'_, 1>

Bit 1 - WritebackDoneHead Interrupt Enable

pub fn start_of_frame(&mut self) -> START_OF_FRAME_W<'_, 2>

Bit 2 - StartofFrame Interrupt Enable

pub fn resume_detected(&mut self) -> RESUME_DETECTED_W<'_, 3>

Bit 3 - ResumeDetected Interrupt Enable

pub fn unrecoverable_error(&mut self) -> UNRECOVERABLE_ERROR_W<'_, 4>

Bit 4 - UnrecoverableError Interrupt Enable

pub fn frame_number_overflow(&mut self) -> FRAME_NUMBER_OVERFLOW_W<'_, 5>

Bit 5 - FrameNumberOverflow Interrupt Enable

pub fn root_hub_status_change(&mut self) -> ROOT_HUB_STATUS_CHANGE_W<'_, 6>

Bit 6 - RootHubStatusChange Interrupt Enable

pub fn master_interrupt_enable(&mut self) -> MASTER_INTERRUPT_ENABLE_W<'_, 31>

Bit 31 - MasterInterruptEnable

A ‘0’ writtern to this field is ignored by HC. A ‘1’ written to this field enables interrupt generation due to events specified in the other bits of this register. This is used by HCD as Master Interrupt Enable.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<HC_INTERRUPT_ENABLE_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<HC_INTERRUPT_ENABLE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<HC_INTERRUPT_ENABLE_SPEC>> for W

fn from(writer: W<HC_INTERRUPT_ENABLE_SPEC>) -> Self

Converts to this type from the input type.