Enum mnemos_d1_core::dmac::ChannelMode

pub enum ChannelMode {
    Wait,
    Handshake,
}

DMA channel modes.

These configure the behavior of a DMA channel when a transfer completes. The source and destination modes of a Channel may be configured using Channel::set_channel_modes.

Variants

Wait

DMA transfer wait mode.

In this mode, the DMAC will wait for a configurable number of clock cycles before automatically starting the next transfer.

The Allwinner documentation for the D1 describes this mode as follows:

• When the DMAC detects a valid external request signal, the DMAC starts to operate the peripheral device. The internal DRQ always holds high before the transferred data amount reaches the transferred block length.
• When the transferred data amount reaches the transferred block length, the internal DRQ pulls low automatically.
• The internal DRQ holds low for certain clock cycles (WAIT_CYC), and then the DMAC restarts to detect the external requests. If the external request signal is valid, then the next transfer starts.

Handshake

DMA transfer handshake mode.

In this mode, the DMAC sends the peripheral a DMA Ack signal when the transfer completes, and waits for the peripheral to pull the DMA Active signal low before starting the next transfer.

The Allwinner documentation for the D1 describes this mode as follows:

• When the DMAC detects a valid external request signal, the DMAC starts to operate the peripheral device. The internal DRQ always holds high before the transferred data amount reaches the transferred block length.
• When the transferred data amount reaches the transferred block length, the internal DRQ will be pulled down automatically. For the last data transfer of the block, the DMAC sends a DMA Last signal with the DMA commands to the peripheral device. The DMA Last signal will be packed as part of the DMA commands and transmitted on the bus. It is used to inform the peripheral device that it is the end of the data transfer for the current DRQ.
• When the peripheral device receives the DMA Last signal, it can judge that the data transfer for the current DRQ is finished. To continue the data transfer, it sends a DMA Active signal to the DMAC. Note: One DMA Active signal will be converted to one DRQ signal in the DMA module. To generate multiple DRQs, the peripheral device needs to send out multiple DMA Active signals via the bus protocol.
• When the DMAC received the DMA Active signal, it sends back a DMA ACK signal to the peripheral device.
• When the peripheral device receives the DMA ACK signal, it waits for all the operations on the local device completed, and both the FIFO and DRQ status refreshed. Then it invalidates the DMA Active signal.
• When the DMAC detects the falling edge of the DMA Active signal, it invalidates the corresponding DMA ACK signal, and restarts to detect the external request signals. If a valid request signal is detected, the next data transfer starts.

Trait Implementations

impl Clone for ChannelMode

fn clone(&self) -> ChannelMode

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ChannelMode

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for ChannelMode