Enum mnemos_d1_core::trap::Exception
source · #[repr(usize)]pub enum Exception {
Show 14 variants
InstAddrMisaligned = 0,
InstAccessFault = 1,
IllegalInst = 2,
Breakpoint = 3,
LoadAddrMisaligned = 4,
LoadAccessFault = 5,
StoreAddrMisaligned = 6,
StoreAccessFault = 7,
UModeEnvCall = 8,
SModeEnvCall = 9,
MModeEnvCall = 11,
InstPageFault = 12,
LoadPageFault = 13,
StorePageFault = 15,
}
Expand description
RISC-V exception causes.
If the interrupt bit (the highest bit) in the mcause
register is 0, the
rest of the mcause
register is interpreted as an exception cause.
See “3.1.20 Machine Cause Register (mcause
)” in RISC-V rivileged
Architectures, v1.10.
Variants§
InstAddrMisaligned = 0
Instruction address misaligned
InstAccessFault = 1
Instruction access fault
IllegalInst = 2
Illegal instruction
Breakpoint = 3
Breakpoint
LoadAddrMisaligned = 4
Load address misaligned
LoadAccessFault = 5
Load access fault
StoreAddrMisaligned = 6
Store/AMO address misaligned
StoreAccessFault = 7
Store/AMO access fault
UModeEnvCall = 8
Environment call from U-mode
SModeEnvCall = 9
Environment call from S-mode
MModeEnvCall = 11
Environment call from M-mode
InstPageFault = 12
Instruction page fault
LoadPageFault = 13
Load page fault
StorePageFault = 15
Store/AMO page fault
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impl Copy for Exception
impl Eq for Exception
impl StructuralPartialEq for Exception
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impl Freeze for Exception
impl RefUnwindSafe for Exception
impl Send for Exception
impl Sync for Exception
impl Unpin for Exception
impl UnwindSafe for Exception
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