Enum mnemos_d1_core::trap::Interrupt
source · #[repr(usize)]pub enum Interrupt {
UserSw = 0,
SupervisorSw = 1,
MachineSw = 3,
UserTimer = 4,
SupervisorTimer = 5,
MachineTimer = 7,
UserExt = 8,
SupervisorExt = 9,
MachineExt = 11,
}
Expand description
RISC-V interrupt causes.
If the interrupt bit (the highest bit) in the mcause
register is 1, the
rest of the mcause
register is interpreted as an interrupt cause.
See “3.1.20 Machine Cause Register (mcause
)” in RISC-V Privileged
Architectures, v1.10.
Variants§
UserSw = 0
User software interrupt
SupervisorSw = 1
Supervisor software interrupt
MachineSw = 3
Machine software interrupt
UserTimer = 4
User timer interrupt
SupervisorTimer = 5
Supervisor timer interrupt
MachineTimer = 7
Machine timer interrupt
UserExt = 8
User external interrupt
SupervisorExt = 9
Supervisor external interrupt
MachineExt = 11
Machine external interrupt
Trait Implementations§
impl Copy for Interrupt
impl Eq for Interrupt
impl StructuralPartialEq for Interrupt
Auto Trait Implementations§
impl Freeze for Interrupt
impl RefUnwindSafe for Interrupt
impl Send for Interrupt
impl Sync for Interrupt
impl Unpin for Interrupt
impl UnwindSafe for Interrupt
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